JPS64851B2 - - Google Patents
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- Publication number
- JPS64851B2 JPS64851B2 JP57201211A JP20121182A JPS64851B2 JP S64851 B2 JPS64851 B2 JP S64851B2 JP 57201211 A JP57201211 A JP 57201211A JP 20121182 A JP20121182 A JP 20121182A JP S64851 B2 JPS64851 B2 JP S64851B2
- Authority
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- Japan
- Prior art keywords
- terminal
- node
- junction
- input
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
- H03K19/1954—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
- H03K19/1956—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current using an inductorless circuit
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、ジヨセフソン接合を用いた高集積論
理回路に関し、とくに３接合電流注入型論理回路
を提供せんとするものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to highly integrated logic circuits using Josephson junctions, and particularly to a three-junction current injection type logic circuit.
従来２個の接合を用いた第１図ａのような
DCL（Direct Coupled Logic）回路が知られてい
た。これは一般にOR論理機能をもつもので、参
考文献、IEDM Technical Digest（Washington
Ｄ，C.，Dec.3―５，1979）の482―484頁に開示
されている。
Conventionally, as shown in Fig. 1a using two joints,
The DCL (Direct Coupled Logic) circuit was known. This generally has an OR logic function and can be found in the reference IEDM Technical Digest (Washington).
D., C., Dec. 3-5, 1979), pages 482-484.
このDCL回路は、入出力しきい値特性が第
１図ｂのように勾配―１の直線で表わされるごと
く利得が小さい、入力端は同図ａで有限のイン
ピーダンスR1によつて接地され入力インピーダ
ンスがゼロにならないため、回路がスイツチする
前の状態で入出力分離がわるい、という欠点を持
つていた。 This DCL circuit has a small gain as shown by the input/output threshold characteristic shown by a straight line with a slope of -1 as shown in Figure 1b. Since the impedance does not become zero, it has the disadvantage of poor input/output separation before the circuit is switched.
本発明は上記のような従来回路の欠点をなく
し、利得を１から３に増倍すると共に、入力イン
ピーダンスをゼロにできる、新しい回路を提供し
ようとするものである。
The present invention aims to eliminate the drawbacks of the conventional circuits as described above, and to provide a new circuit that can multiply the gain from 1 to 3 and reduce the input impedance to zero.
以下、本発明を実施例と共に詳細に説明する。
本発明は第２図ａに示すごとく、前記したDCL
回路に加えてその入力端に直列抵抗R0とジヨセ
フソン接合J0を用いた結線をもつている。入力端
は直接接合J0によつて接地されるため、接合J0が
スイツチしない状態（ゼロ電圧状態または超電導
状態）では必ず抵抗ゼロの状態にある。
Hereinafter, the present invention will be explained in detail together with examples.
As shown in FIG. 2a, the present invention provides the above-mentioned DCL
In addition to the circuit, it has a connection using a series resistor R 0 and Josephson junction J 0 at its input end. Since the input terminal is directly grounded by the junction J 0 , it is always in a state of zero resistance when the junction J 0 is not switched (zero voltage state or superconducting state).
この第２図ａの結線の入出力しきい値特性は以
下の３つの方程式によつて記述される。電源電流
をIg、入力電流をI0とする。まず第１の方程式は
R1R2／ΣRpRqIg＋I0＞In0 ……(1)
と表わされる。ここにIn0は接合J0の最大超電導
トンネル電流をあらわす。また分母の記号ΣRpRq
は次式
ΣRpRq＝R0R1＋R1R2＋R2R0 ……(2)
によつて定義される量である。第２の方程式は
R1｛（RJ0＋R0）Ig＋RJ0I0｝／RJ0（R1＋R2）＋ΣRpR
q＞In2……(3)
である。ここにIn2は接合J2の最大超電導トンネ
ル電流、RJ0は接合J0がスイツチした状態におけ
る接合抵抗の値をあらわす。もし、
RJ0≫R0，R1，R2 ……(4)
の近似が許されるならば、(3)式は
（R1／R1＋R2）（Ig＋I0）＞In2 ……（3′）
によつて近似される。第３の方程式は
（RJ0＋R0＋R1）（RJ2＋αR2）Ig−αRJ0R1I0
／RJ2（RJ0＋R0＋R1）＋α｛RJ0（R1＋R2）＋ΣRpRq｝
＞In1……(5)
である。ここにIn1は接合J1の最大超電導トンネ
ル電流、RJ2は接合J2がスイツチした状態におけ
る接合抵抗の値をあらわす。また分母、分子に含
まれる記号αは次式
α＝１＋RJ2／RL ……(6)
によつて定義される量である。もし、
RJ2≫R0，R1，R2，RL
RJ0≫R0，R1，R2，RL ……(7)
の近似が許されるならば、(5)式は
（RL＋R2）Ig−R1I0／RL＋R1＋R2＞In1……(8)
によつて近似される。 The input/output threshold characteristics of the connection shown in FIG. 2a are described by the following three equations. Let the power supply current be I g and the input current I 0 . First, the first equation is expressed as R 1 R 2 /ΣR p R q I g +I 0 >I n0 (1). Here I n0 represents the maximum superconducting tunneling current of the junction J 0 . Also, the denominator symbol ΣR p R q
is a quantity defined by the following equation ΣR p R q = R 0 R 1 + R 1 R 2 + R 2 R 0 ...(2). The second equation is R 1 {(R J0 + R 0 ) I g + R J0 I 0 }/R J0 (R 1 + R 2 ) + ΣR p R
q > I n2 ...(3). Here, I n2 represents the maximum superconducting tunneling current of the junction J 2 , and R J0 represents the value of the junction resistance when the junction J 0 is switched. If the approximation of R J0 ≫R 0 , R 1 , R 2 ...(4) is allowed, equation (3) becomes (R 1 /R 1 +R 2 )(I g +I 0 )>I n2 ... …(3′) is approximated by. The third equation is (R J0 +R 0 +R 1 )(R J2 +αR 2 )I g −αR J0 R 1 I 0
/R J2 (R J0 +R 0 +R 1 )+α{R J0 (R 1 +R 2 )+ΣR p R q }
＞I n1 ...(5). Here, I n1 represents the maximum superconducting tunneling current of the junction J 1 , and R J2 represents the value of the junction resistance when the junction J 2 is switched. Further, the symbol α included in the denominator and numerator is a quantity defined by the following formula α=1+R J2 /R L (6). If the approximation of R J2 ≫R 0 , R 1 , R 2 , R L R J0 ≫R 0 , R 1 , R 2 , R L ...(7) is allowed, equation (5) becomes (R L + R 2 ) I g −R 1 I 0 / R L + R 1 + R 2 > I n1 ...(8).
この回路が駆動できるためには、次の方程式が
成立することが前提条件となる。すなわち、
In0／R1R2＝In1／R2（R0＋R1）＝In2／R0R1 ……(9)
が必要である。 In order for this circuit to be able to drive, it is a prerequisite that the following equation holds true. That is, I n0 /R 1 R 2 = I n1 /R 2 (R 0 +R 1 ) = I n2 /R 0 R 1 (9) is required.
条件式(9)を満足する回路パラメータとして本発
明者らは
R0＝R1＝R2＝1Ω
In0＝In2＝30μA
In1＝60μA ……(10)
の条件を選んだ。このとき、一実施例として、
RJ0＝RJ2＝567Ω
RJ1＝283Ω
RL＝8Ω ……(11)
に設定した。このときの入出しきい値特性は、
(1)，(3)，(5)式から計算される。結果は第２図ｂに
示すごとく、有効動作範囲（斜線部分）において
勾配―1/3の直線が臨界線となり、利得が３と
DCL回路よりも３倍大きい。 The present inventors selected the following conditions as circuit parameters satisfying conditional expression (9): R 0 =R 1 =R 2 =1Ω I n0 =I n2 =30 μA I n1 =60 μA (10). At this time, as an example, the following settings were made: R J0 = R J2 = 567 Ω R J1 = 283 Ω R L = 8 Ω (11). The input/output threshold characteristics at this time are:
Calculated from equations (1), (3), and (5). As shown in Figure 2b, the result is that in the effective operating range (shaded area), the straight line with slope -1/3 becomes the critical line, and the gain is 3.
3 times larger than DCL circuit.
次に本発明の第２の実施例について説明する。
第２の例では、第３図ａに示すごとく、電源電流
Ig2を第２図ａの結線に追加したものである。区
別のために先の図と同じ電源電流をIg1、新たに
追加した分をIg2と定義する。この回路の入出力
しきい値特性は以下の３つの方程式によつて記述
される。第１の方程式は(1)式と同じであり、
R1R2／ΣRpRqIg1＋I0＞In0 ……(12)
である。第２の方程式は
R1｛（RJ0＋R0）Ig＋RJ0I0｝／RJ0（R1＋R2）＋ΣRpRq
＞（In2−Ig2）
……（13）
である。第３の方程式は
（RJ2＋αR2）（RJ0＋R0＋R1）Ig1＋RJ2（RJ0＋R0＋R1
）Ig2−αRJ0R1I0／RJ2（RJ0＋R0＋R1）＋α｛RJ0（R1
＋R2）＋ΣRpRq｝＞In1……（14）
である。 Next, a second embodiment of the present invention will be described.
In the second example, as shown in Figure 3a, the power supply current
I g2 is added to the connection shown in Figure 2a. For distinction, the same power supply current as in the previous figure is defined as I g1 , and the newly added current is defined as I g2 . The input/output threshold characteristics of this circuit are described by the following three equations. The first equation is the same as equation (1), and is R 1 R 2 /ΣR p R q I g1 +I 0 >I n0 (12). The second equation is R 1 {(R J0 + R 0 ) I g + R J0 I 0 }/R J0 (R 1 + R 2 ) + ΣR p R q
> (I n2 − I g2 ) ...(13). The third equation is (R J2 + αR 2 ) (R J0 + R 0 + R 1 ) I g1 + R J2 (R J0 + R 0 + R 1
)I g2 −αR J0 R 1 I 0 /R J2 (R J0 +R 0 +R 1 )+α{R J0 (R 1
+R 2 )+ΣR p R q }>I n1 ...(14).
この回路が駆動できるためには、次の方程式が
成立することが前提条件となる。すなわち、
In0／R1R2＝In1／R2（R0＋R1）＝In2−Ig2／R0R1……
（15）
が必要である。 In order for this circuit to be able to drive, it is a prerequisite that the following equation holds true. That is, I n0 /R 1 R 2 = I n1 / R 2 (R 0 + R 1 ) = I n2 − I g2 / R 0 R 1 ...
(15) is required.
条件式（15）を満足する回路パラメータとして
本発明者らは
R0＝R1＝R2＝1Ω
In0＝30μA
In1＝In2＝60μA
Ig2＝30μA ……（16）
の条件を選んだ。このとき、一実施例として、
RJ0＝567Ω
RJ1＝RJ2＝283Ω
RL＝8Ω ……（17）
に設定した。このときの入力出力しきい値特性は
(12)，（13），（14）式から計算される。結果は第３
図ｂに示すごとく、有効動作範囲（斜線部分）に
おいて勾配―1/3の直線が臨界線となり、利得が
３とDCL回路よりも３倍大きい。 As circuit parameters that satisfy conditional expression (15), the inventors selected the following conditions: R 0 = R 1 = R 2 = 1Ω I n0 = 30 μA I n1 = I n2 = 60 μA I g2 = 30 μA (16) is. At this time, as an example, the following settings were made: R J0 = 567Ω R J1 = R J2 = 283Ω R L = 8Ω (17). The input/output threshold characteristics at this time are
Calculated from equations (12), (13), and (14). The result is the third
As shown in Figure b, in the effective operating range (shaded area), the straight line with slope -1/3 becomes the critical line, and the gain is 3, which is 3 times larger than the DCL circuit.
この第２の実施例は第１の実施例くらべて動作
マージンが広い。すなわち、第１の実施例ではIg
の設定可能範囲が90μAのうちの27％であるのに
対し、第２の実施例では120μAのうちの38％に増
大している。さらに出力電流も大きくできること
は明らかである。 This second embodiment has a wider operating margin than the first embodiment. That is, in the first embodiment, I g
The settable range is 27% of 90 μA, whereas in the second embodiment, it increases to 38% of 120 μA. It is clear that the output current can also be increased.
以上述べたごとく本発明によれば、比較的少な
い接合の使用個数において、高利得、入出力
分離完全、という特長をもつ、ジヨセフソン論理
回路を構成できる。このため、ジヨセフソン接合
を使用する超高速計算機への適用が期待できる。
As described above, according to the present invention, a Josephson logic circuit having the features of high gain and complete input/output separation can be constructed using a relatively small number of junctions. Therefore, it can be expected to be applied to ultra-high-speed computers using Josephson junctions.
第１図は従来公知のDCL回路の結線ａとその
入出力特性のしきい値ｂを示す図、第２図は本発
明の１実施例の回路の結線図とそのしきい値特性
を示す図、第３図は本発明の他実施例の回路の結
線図とそのしきい値特性を示す図である。
１…入力端、２…ブリツジ形回路の一端、３…
電源端、４…出力端、R0…入力抵抗、R1…ブリ
ツジの第２辺にある抵抗、R2…ブリツジの第３
辺にある抵抗、RL…負荷抵抗、J0…入力端にあ
るジヨセフソン接合、J1…ブリツジの第１辺にあ
る抵抗、J2…ブリツジの第４辺にある抵抗、I0…
入力（信号）電流、Ig…電源電流、Ig1…第１の電
源電流、Ig1…第２の電源電流、In1…接合J1の最
大超電導トンネル電流、In2…接合J2の最大超電
導トンネル電流。
FIG. 1 is a diagram showing the connection a of a conventionally known DCL circuit and the threshold value b of its input/output characteristics, and FIG. 2 is a diagram showing the connection diagram of a circuit according to an embodiment of the present invention and its threshold characteristic. , FIG. 3 is a wiring diagram of a circuit according to another embodiment of the present invention and a diagram showing its threshold characteristics. 1...Input end, 2...One end of the bridge type circuit, 3...
Power supply terminal, 4...Output terminal, R0 ...Input resistance, R1 ...Resistor on the second side of the bridge, R2 ...Third side of the bridge
Resistance on the side, R L ... load resistance, J 0 ... Josephson junction at the input end, J 1 ... resistance on the first side of the bridge, J 2 ... resistance on the fourth side of the bridge, I 0 ...
Input (signal) current, I g ... power supply current, I g1 ... first power supply current, I g1 ... second power supply current, I n1 ... maximum superconducting tunneling current of junction J 1 , I n2 ... maximum of junction J 2 Superconducting tunnel current.
Claims (1)
２の抵抗R2の第１の端子とは共通に第１の節点
に接続され、上記第１のジヨセフソン接合の第２
の端子と第１の抵抗R1の第１の端子とは共通に
第２の節点に接続され、上記第２の抵抗の第２の
端子と第２のジヨセフソン接合J2の第１の端子と
は共通に第３の節点に接続され、上記第１の抵抗
の第２の端子と上記第２のジヨセフソン接合の第
２の端子とは共通に接地され、入力抵抗R0の第
１の端子は上記第２の節点に接続され、入力抵抗
の第２の端子と第３のジヨセフソン接合J0の第１
の端子とは共通に第４の節点に接続され、上記第
３のジヨセフソン接合の第２の端子は接地され、
上記第１の節点に電流源Igが接続され、上記第４
の節点に入力電流源I0が接続され、上記第３の節
点に負荷抵抗RLが接続されていることを特徴と
する３接合電流注入型ジヨセフソン論理回路。1 The first terminal of the first Josephson junction J 1 and the first terminal of the second resistor R 2 are commonly connected to the first node, and the second terminal of the first Josephson junction J 1 is connected to the first node in common.
and the first terminal of the first resistor R 1 are commonly connected to the second node, and the second terminal of the second resistor and the first terminal of the second Josephson junction J 2 are connected in common to the second node. are commonly connected to a third node, the second terminal of the first resistor and the second terminal of the second Josephson junction are commonly grounded, and the first terminal of the input resistor R 0 is connected to the second node above, the second terminal of the input resistor and the first of the third Josephson junction J 0
is commonly connected to the fourth node, and the second terminal of the third Josephson junction is grounded;
A current source I g is connected to the first node, and the fourth
A three-junction current injection type Josephson logic circuit, characterized in that an input current source I 0 is connected to the node, and a load resistor R L is connected to the third node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57201211A JPS5991727A (en) | 1982-11-18 | 1982-11-18 | Three junction current injecting type josephson logical circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57201211A JPS5991727A (en) | 1982-11-18 | 1982-11-18 | Three junction current injecting type josephson logical circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5991727A JPS5991727A (en) | 1984-05-26 |
| JPS64851B2 true JPS64851B2 (en) | 1989-01-09 |
Family
ID=16437187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57201211A Granted JPS5991727A (en) | 1982-11-18 | 1982-11-18 | Three junction current injecting type josephson logical circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5991727A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59188235A (en) * | 1983-04-11 | 1984-10-25 | Nec Corp | Current injection type logical gate circuit using josephson effect |
| US5233243A (en) * | 1991-08-14 | 1993-08-03 | Westinghouse Electric Corp. | Superconducting push-pull flux quantum logic circuits |
-
1982
- 1982-11-18 JP JP57201211A patent/JPS5991727A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5991727A (en) | 1984-05-26 |
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