JPS6489373A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6489373A
JPS6489373A JP24655387A JP24655387A JPS6489373A JP S6489373 A JPS6489373 A JP S6489373A JP 24655387 A JP24655387 A JP 24655387A JP 24655387 A JP24655387 A JP 24655387A JP S6489373 A JPS6489373 A JP S6489373A
Authority
JP
Japan
Prior art keywords
region
type
layer
diode
diffused region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24655387A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Hibino
Akihisa Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24655387A priority Critical patent/JPS6489373A/en
Publication of JPS6489373A publication Critical patent/JPS6489373A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To improve Q of a diode by forming a first conductivity type low resistance impurity diffused region between a second conductivity type impurity diffused region and a second conductivity impurity diffused region for forming the diode in a first conductivity type high resistance epitaxially grown layer. CONSTITUTION:A high resistance N<+> type epitaxially grown layer 2 is formed on an N<+> type semiconductor substrate region 1, and a P<+> type diffused region 4 is formed on the periphery of the layer 2. A P<+> type diffused region 3 which is selectively diffused in the layer 2 and operates as a diode is formed by forming a P-N junction to the layer 2. An N<+> type diffused region 5 is formed in the layer 2 between the region 3 as the diode and the region 4 on the periphery. Thus, a device configuration of high quality of high Q is obtained to improve high frequency characteristic. The breakdown strength of the device can be also improved.
JP24655387A 1987-09-29 1987-09-29 Semiconductor device Pending JPS6489373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24655387A JPS6489373A (en) 1987-09-29 1987-09-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24655387A JPS6489373A (en) 1987-09-29 1987-09-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6489373A true JPS6489373A (en) 1989-04-03

Family

ID=17150127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24655387A Pending JPS6489373A (en) 1987-09-29 1987-09-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6489373A (en)

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