JPS6489595A - Manufacture of wiring board - Google Patents
Manufacture of wiring boardInfo
- Publication number
- JPS6489595A JPS6489595A JP24712887A JP24712887A JPS6489595A JP S6489595 A JPS6489595 A JP S6489595A JP 24712887 A JP24712887 A JP 24712887A JP 24712887 A JP24712887 A JP 24712887A JP S6489595 A JPS6489595 A JP S6489595A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- peeled
- side wall
- polyimide
- glass substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 7
- 239000010410 layer Substances 0.000 abstract 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 4
- 229910052802 copper Inorganic materials 0.000 abstract 4
- 239000010949 copper Substances 0.000 abstract 4
- 239000004642 Polyimide Substances 0.000 abstract 3
- 239000011521 glass Substances 0.000 abstract 3
- 229920001721 polyimide Polymers 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 2
- 239000011229 interlayer Substances 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 2
- 229910052751 metal Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
PURPOSE:To enable a support substrate to be peeled off easily, making the outer periphery and/or side wall of the support substrate vitreous at least in the surface rough, and the other part smooth, by providing the support substrate with a copper layer, and by forming thereon a multilayer wiring consisting of wiring conductor and insulating resin such as polyimide. CONSTITUTION:The side wall and the substrate end of a glass substrate 1 having a smooth surface 2 are made rough 3 with a rotary whetstone. Next, a copper layer 4 is formed on the surface of the glass substrate and on the side wall. A resist layer is formed on the surface of the copper layer 4 and turned into a resist pattern by exposure and development, and a part free of resist is plated with copper; then, the resist is peeled off to form an interlayer connection metal column 5. After a polyimide layer 6 is provided, the polyimide is flattened to allow the interlayer connection metal column 5 to be exposed, resulting in formation of wiring conductor 7. Such steps are repeated required times to allow a multilayer structure. Then, a part finally forming the product is peeled off from the glass substrate, thus obtaining a multilayer wiring board 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24712887A JPH081988B2 (en) | 1987-09-30 | 1987-09-30 | Manufacturing method of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24712887A JPH081988B2 (en) | 1987-09-30 | 1987-09-30 | Manufacturing method of wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6489595A true JPS6489595A (en) | 1989-04-04 |
| JPH081988B2 JPH081988B2 (en) | 1996-01-10 |
Family
ID=17158848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24712887A Expired - Lifetime JPH081988B2 (en) | 1987-09-30 | 1987-09-30 | Manufacturing method of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH081988B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06334343A (en) * | 1992-09-04 | 1994-12-02 | Hitachi Ltd | Manufacture of multilayered wiring board and high density multilayered wiring board |
| US7187072B2 (en) | 1994-03-18 | 2007-03-06 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
| EP2287897A3 (en) * | 1996-05-27 | 2011-11-02 | Dai Nippon Printing Co., Ltd. | Circuit member for semiconductor device, semiconductor device using the same, and process for producing said circuit member and said semiconductor device |
| WO2020105236A1 (en) * | 2018-11-20 | 2020-05-28 | 三井金属鉱業株式会社 | Multilayer body |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100209259B1 (en) * | 1996-04-25 | 1999-07-15 | 이해규 | Ic card and method for manufacture of the same |
-
1987
- 1987-09-30 JP JP24712887A patent/JPH081988B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06334343A (en) * | 1992-09-04 | 1994-12-02 | Hitachi Ltd | Manufacture of multilayered wiring board and high density multilayered wiring board |
| US7187072B2 (en) | 1994-03-18 | 2007-03-06 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
| EP2287897A3 (en) * | 1996-05-27 | 2011-11-02 | Dai Nippon Printing Co., Ltd. | Circuit member for semiconductor device, semiconductor device using the same, and process for producing said circuit member and said semiconductor device |
| WO2020105236A1 (en) * | 2018-11-20 | 2020-05-28 | 三井金属鉱業株式会社 | Multilayer body |
| TWI717107B (en) * | 2018-11-20 | 2021-01-21 | 日商三井金屬鑛業股份有限公司 | Layered body |
| JPWO2020105236A1 (en) * | 2018-11-20 | 2021-09-30 | 三井金属鉱業株式会社 | Laminate |
| US12193153B2 (en) | 2018-11-20 | 2025-01-07 | Mitsui Mining & Smelting Co., Ltd. | Multilayer body |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH081988B2 (en) | 1996-01-10 |
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