JPS649734B2 - - Google Patents

Info

Publication number
JPS649734B2
JPS649734B2 JP56213989A JP21398981A JPS649734B2 JP S649734 B2 JPS649734 B2 JP S649734B2 JP 56213989 A JP56213989 A JP 56213989A JP 21398981 A JP21398981 A JP 21398981A JP S649734 B2 JPS649734 B2 JP S649734B2
Authority
JP
Japan
Prior art keywords
package
semiconductor chip
pads
wire
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56213989A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58114444A (ja
Inventor
Hidehiko Akasaki
Takehisa Tsujimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56213989A priority Critical patent/JPS58114444A/ja
Publication of JPS58114444A publication Critical patent/JPS58114444A/ja
Publication of JPS649734B2 publication Critical patent/JPS649734B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)
JP56213989A 1981-12-26 1981-12-26 半導体装置 Granted JPS58114444A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56213989A JPS58114444A (ja) 1981-12-26 1981-12-26 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56213989A JPS58114444A (ja) 1981-12-26 1981-12-26 半導体装置

Publications (2)

Publication Number Publication Date
JPS58114444A JPS58114444A (ja) 1983-07-07
JPS649734B2 true JPS649734B2 (mo) 1989-02-20

Family

ID=16648405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56213989A Granted JPS58114444A (ja) 1981-12-26 1981-12-26 半導体装置

Country Status (1)

Country Link
JP (1) JPS58114444A (mo)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02196448A (ja) * 1989-01-25 1990-08-03 Nec Corp 半導体装置
KR950012290B1 (ko) * 1993-05-14 1995-10-16 삼성전자주식회사 메모리 모듈

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108369A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Electronic components

Also Published As

Publication number Publication date
JPS58114444A (ja) 1983-07-07

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