KR920020719A - 반도체 메로리의 제조방법 - Google Patents
반도체 메로리의 제조방법 Download PDFInfo
- Publication number
- KR920020719A KR920020719A KR1019920006650A KR920006650A KR920020719A KR 920020719 A KR920020719 A KR 920020719A KR 1019920006650 A KR1019920006650 A KR 1019920006650A KR 920006650 A KR920006650 A KR 920006650A KR 920020719 A KR920020719 A KR 920020719A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor memory
- conductive film
- manufacturing semiconductor
- memory cell
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 일실시예를 순차로 도시한 측단면도.
Claims (1)
- 메모리셀부와 주변회로부를 가지고 있으며, 트랜지스터와 커패시터로 메모리셀이 구성되어 있는 반도체메모리의 제조방법에 있어서, 상기 커패시터의 플레이트전극으로 하기 위한 도전막을 형성하고, 상기 도전막을 상기 메모리셀부에 있어서만 상기 플레이트전극의 패턴으로 가공하고, 저융점절연막으로 상기 도전막상을 평탄화하고, 상기 주변회로부에 있어서의 상기 저융점절연막과 상기 도전막을 제거하는 반도체메모리의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03126889A JP3079637B2 (ja) | 1991-04-30 | 1991-04-30 | 半導体メモリの製造方法 |
| JP91-126,889 | 1991-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR920020719A true KR920020719A (ko) | 1992-11-21 |
Family
ID=14946369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920006650A Withdrawn KR920020719A (ko) | 1991-04-30 | 1992-04-21 | 반도체 메로리의 제조방법 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5346843A (ko) |
| EP (1) | EP0511631B1 (ko) |
| JP (1) | JP3079637B2 (ko) |
| KR (1) | KR920020719A (ko) |
| DE (1) | DE69211608T2 (ko) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01230081A (ja) * | 1988-03-10 | 1989-09-13 | Nec Corp | 現像装置 |
| JP2757733B2 (ja) * | 1992-03-25 | 1998-05-25 | 松下電器産業株式会社 | 半導体装置の製造方法 |
| JP2643870B2 (ja) * | 1994-11-29 | 1997-08-20 | 日本電気株式会社 | 半導体記憶装置の製造方法 |
| JP6408372B2 (ja) * | 2014-03-31 | 2018-10-17 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像装置及びその駆動制御方法、並びに、電子機器 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153158A (ja) * | 1984-01-23 | 1985-08-12 | Oki Electric Ind Co Ltd | キャパシタ誘電体膜の製造方法 |
| JPH0666437B2 (ja) * | 1987-11-17 | 1994-08-24 | 富士通株式会社 | 半導体記憶装置及びその製造方法 |
| JPH0221652A (ja) * | 1988-07-08 | 1990-01-24 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US5043780A (en) * | 1990-01-03 | 1991-08-27 | Micron Technology, Inc. | DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance |
| JP2519569B2 (ja) * | 1990-04-27 | 1996-07-31 | 三菱電機株式会社 | 半導体記憶装置およびその製造方法 |
-
1991
- 1991-04-30 JP JP03126889A patent/JP3079637B2/ja not_active Expired - Fee Related
-
1992
- 1992-04-21 KR KR1019920006650A patent/KR920020719A/ko not_active Withdrawn
- 1992-04-21 US US07/871,705 patent/US5346843A/en not_active Expired - Fee Related
- 1992-04-28 EP EP92107215A patent/EP0511631B1/en not_active Expired - Lifetime
- 1992-04-28 DE DE69211608T patent/DE69211608T2/de not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3079637B2 (ja) | 2000-08-21 |
| JPH04329668A (ja) | 1992-11-18 |
| DE69211608D1 (de) | 1996-07-25 |
| DE69211608T2 (de) | 1997-02-13 |
| EP0511631B1 (en) | 1996-06-19 |
| EP0511631A1 (en) | 1992-11-04 |
| US5346843A (en) | 1994-09-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19920421 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |