KR970077700A - 박층의 반도체 재료를 제조하는 방법 - Google Patents

박층의 반도체 재료를 제조하는 방법 Download PDF

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KR970077700A
KR970077700A KR1019970018788A KR19970018788A KR970077700A KR 970077700 A KR970077700 A KR 970077700A KR 1019970018788 A KR1019970018788 A KR 1019970018788A KR 19970018788 A KR19970018788 A KR 19970018788A KR 970077700 A KR970077700 A KR 970077700A
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semiconductor material
wafer
thin layer
manufacturing
heat treatment
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KR100704107B1 (ko
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버나드 아스파
미쉘 브리엘
씨에리 포메이로
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삐에르 쇼위죠
꼼미싸레 아 라네르기 아토미크
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70541Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices
    • H10P54/50Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
    • H10P54/52Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7432Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612Composite web or sheet

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Micromachines (AREA)

Abstract

본 발명은 박층의 반도체 재료를 제조하는 방법에 관한 것으로, 본 발명에 따른 박층의 반도체 재료의 제조방법은, 반도체 웨이퍼(wafer) 평탄면(2)를 통하여 이온을 주입하여 미소공동(microcavity)층을 형성하는 단계로서, 이온 선량(ion dose)이 상기한 평탄면에 기포가 형성되지 않도록 하는 특정 범위 내에 있는 단계; 미소공동(microcavity)을 유착시키는 열처리 단계; 박층(6)에 적어도 하나의 전자부품(electronic component)을 형성하는 단계; 및 웨이퍼의 나머지 부분으로부터 박층(6)을 분리하는 단계를 포함하는 것으로 특징으로 한다.

Description

박층의 반도체 재료를 제조하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 방법에 있어서, 웨이퍼를 두 부분으로 분리시키는 단계를 도시한 개략도이다.

Claims (12)

  1. 평탄면을 지닌 상기한 반도체 재료 웨이퍼로부터 박층의 반도체 재료를 제조하는 방법으로서, 상기한 평탄면에 비활성 기체 이온 또는 수소 이온 중에서 선택된 이온을, 특정 온도와 특정 선량으로 조사하여, 이온들의 평균 투과 깊이에 근사한 깊이에 위치한 소위 기준면(reference plane)이라는 평면에 미소공동을 형성하는 이온 주입 단계; 및 상기한 기준면을 따라, 웨이퍼를 두 부분으로 분리하기에 충분한 온도에서 열처리하여, 박층을 구성하는 평탄면의 한쪽에 위치한 부분을 분리하는 열처리 단계를 포함하며; -상기한 이온 주입 단계는, 기준면을 따라 웨이퍼를 분열시키기에 충분한 미소공동을 생성할 수 있는 최저 선량과, 열처리 단계에서 웨이퍼의 분리가 일어나게 하고 최고 선량 즉, 임계 선량(critical dose)과의 사이의 이온 선량으로 수행되며; -열처리 단계 후에, 혹은 열처리 단계 중에, 기준면을 따라, 웨이퍼를 두 부분으로 분리는 분리 단계가 제공되며, 이 분리 단계는 웨이퍼의 두 부분 사이에 기계적 힘을 인가하여 수행됨을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  2. 제1항에 있어서, 열처리 단계와 분리 단계와의 사이에서, 박층을 형성하기 전에, 웨이퍼의 일부에 적어도 하나의 전자 부품 전부 또는 일부를 배설하는 단계를 포함하는 것을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  3. 제2항에 있어서, 상기 한 전자부품은 상기한 열처리 단계에서의 온도보다 더 낮은 온도에서 열처리하여 배설됨을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  4. 제1항에 있어서, 분리 단계 직전에, 상기한 웨이퍼를 상기한 평탄면 측에서, 지지체에 밀착시켜 단단하게 고정시키는 추가 공정을 더 포함하며, 이 지지체를 통해 기계적인 힘이 인가됨을 특징으로 하는 박층의 반도체 제조 방법.
  5. 제4항에 있어서, 상기한 지지체는 유연성 지지체임을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  6. 제5항에 있어서, 상기한 유연성 지지체는 Kapton(R)시트임을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  7. 제4항에 있어서, 상기한 지지체는 강성의 지지체임을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  8. 제7항에 있어서, 상기한 강성의 지지체는 산화처리된 실리콘 웨이퍼임을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  9. 제1항에 있어서, 상기한 반도체 재료 웨이퍼는 단결정성 실리콘으로 구성됨을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  10. 제1항에 있어서, 상기한 반도체 재료 웨이퍼는 비반도체 재료층으로 피복되어 있음을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  11. 제10항에 있어서, 비반도체 재료는 유전체 재료임을 특징으로 하는 박층의 반도체 재료의 제조 방법.
  12. 제1항 내지 제11항 중 어느 한 항에 있어서, 분리 단계에서 인가되는 기계적 힘은 인장력 및/또는 전단 응력 및/또는 굽힙력임을 특징으로 하는 박층의 반도체 재료의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970018788A 1996-05-15 1997-05-15 박층의반도체재료를제조하는방법 Expired - Lifetime KR100704107B1 (ko)

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FR9606086 1996-05-15
FR96-06086 1996-05-15
FR9606086A FR2748851B1 (fr) 1996-05-15 1996-05-15 Procede de realisation d'une couche mince de materiau semiconducteur

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KR100704107B1 KR100704107B1 (ko) 2007-07-06

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US (7) US6020252A (ko)
EP (2) EP1768176A3 (ko)
JP (2) JP3517080B2 (ko)
KR (1) KR100704107B1 (ko)
DE (1) DE69738608T2 (ko)
FR (1) FR2748851B1 (ko)
MY (1) MY125679A (ko)
SG (1) SG52966A1 (ko)
TW (1) TW366527B (ko)

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US6809009B2 (en) 2004-10-26
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