SG49705A1 - Basic cell architecture for mask programmable gate array - Google Patents

Basic cell architecture for mask programmable gate array

Info

Publication number
SG49705A1
SG49705A1 SG1996004265A SG1996004265A SG49705A1 SG 49705 A1 SG49705 A1 SG 49705A1 SG 1996004265 A SG1996004265 A SG 1996004265A SG 1996004265 A SG1996004265 A SG 1996004265A SG 49705 A1 SG49705 A1 SG 49705A1
Authority
SG
Singapore
Prior art keywords
programmable gate
gate array
basic cell
cell architecture
mask programmable
Prior art date
Application number
SG1996004265A
Other languages
English (en)
Inventor
El Abbas Gamal
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Publication of SG49705A1 publication Critical patent/SG49705A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/996—Masterslice integrated circuits using combined field effect technology and bipolar technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG1996004265A 1991-06-18 1992-06-11 Basic cell architecture for mask programmable gate array SG49705A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/717,140 US5289021A (en) 1990-05-15 1991-06-18 Basic cell architecture for mask programmable gate array with 3 or more size transistors

Publications (1)

Publication Number Publication Date
SG49705A1 true SG49705A1 (en) 1998-06-15

Family

ID=24880867

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996004265A SG49705A1 (en) 1991-06-18 1992-06-11 Basic cell architecture for mask programmable gate array

Country Status (7)

Country Link
US (1) US5289021A (de)
EP (1) EP0591342B1 (de)
JP (1) JPH06508480A (de)
AU (1) AU2238692A (de)
DE (1) DE69232136T2 (de)
SG (1) SG49705A1 (de)
WO (1) WO1992022924A1 (de)

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US5990502A (en) * 1995-12-29 1999-11-23 Lsi Logic Corporation High density gate array cell architecture with metallization routing tracks having a variable pitch
US5796128A (en) * 1996-07-25 1998-08-18 Translogic Technology, Inc. Gate array with fully wired multiplexer circuits
JP3152635B2 (ja) * 1996-09-09 2001-04-03 三洋電機株式会社 マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器
US6031982A (en) * 1996-11-15 2000-02-29 Samsung Electronics Co., Ltd. Layout design of integrated circuit, especially datapath circuitry, using function cells formed with fixed basic cell and configurable interconnect networks
US6051031A (en) * 1997-02-05 2000-04-18 Virage Logic Corporation Module-based logic architecture and design flow for VLSI implementation
US5780883A (en) * 1997-02-28 1998-07-14 Translogic Technology, Inc. Gate array architecture for multiplexer based circuits
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US6445049B1 (en) * 1997-06-30 2002-09-03 Artisan Components, Inc. Cell based array comprising logic, transfer and drive cells
US6177709B1 (en) 1997-06-30 2001-01-23 Synopsys, Inc. Cell based array having compute/drive ratios of N:1
JP4301462B2 (ja) 1997-09-29 2009-07-22 川崎マイクロエレクトロニクス株式会社 電界効果トランジスタ
US6480032B1 (en) 1999-03-04 2002-11-12 Intel Corporation Gate array architecture
US6974978B1 (en) * 1999-03-04 2005-12-13 Intel Corporation Gate array architecture
US7299459B1 (en) 2000-01-19 2007-11-20 Sabio Labs, Inc. Parser for signomial and geometric programs
US6617621B1 (en) 2000-06-06 2003-09-09 Virage Logic Corporation Gate array architecture using elevated metal levels for customization
US6294927B1 (en) * 2000-06-16 2001-09-25 Chip Express (Israel) Ltd Configurable cell for customizable logic array device
JP2002026296A (ja) * 2000-06-22 2002-01-25 Internatl Business Mach Corp <Ibm> 半導体集積回路装置
US7065727B2 (en) * 2001-04-25 2006-06-20 Barcelona Design, Inc. Optimal simultaneous design and floorplanning of integrated circuit
US6954921B2 (en) * 2002-03-05 2005-10-11 Barcelona Design, Inc. Method and apparatus for automatic analog/mixed signal system design using geometric programming
US20030191611A1 (en) * 2002-04-05 2003-10-09 Hershenson Maria Del Mar Behavioral circuit modeling for geometric programming
US6802050B2 (en) 2002-04-07 2004-10-05 Barcelona Design, Inc. Efficient layout strategy for automated design layout tools
US6909330B2 (en) * 2002-04-07 2005-06-21 Barcelona Design, Inc. Automatic phase lock loop design using geometric programming
US6789246B1 (en) * 2002-04-07 2004-09-07 Barcelona Design, Inc. Method and apparatus for automatic layout of circuit structures
US7093205B2 (en) * 2002-04-10 2006-08-15 Barcelona Design, Inc. Method and apparatus for efficient semiconductor process evaluation
US6988258B2 (en) * 2002-12-09 2006-01-17 Altera Corporation Mask-programmable logic device with building block architecture
US7081772B1 (en) * 2004-06-04 2006-07-25 Altera Corporation Optimizing logic in non-reprogrammable logic devices
US7725858B2 (en) * 2007-06-27 2010-05-25 Intel Corporation Providing a moat capacitance
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
GB201119099D0 (en) 2011-11-04 2011-12-21 Univ York Field-programmable gate array
KR102448030B1 (ko) * 2017-09-21 2022-09-28 삼성디스플레이 주식회사 표시장치
US10707755B1 (en) 2019-01-25 2020-07-07 International Business Machines Corporation Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

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Also Published As

Publication number Publication date
AU2238692A (en) 1993-01-12
DE69232136T2 (de) 2002-03-07
WO1992022924A1 (en) 1992-12-23
EP0591342A4 (de) 1994-03-18
EP0591342A1 (de) 1994-04-13
US5289021A (en) 1994-02-22
EP0591342B1 (de) 2001-10-17
DE69232136D1 (de) 2001-11-22
JPH06508480A (ja) 1994-09-22

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