US20090026501A1 - Enhancement - depletion semiconductor structure and method for making it - Google Patents

Enhancement - depletion semiconductor structure and method for making it Download PDF

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Publication number
US20090026501A1
US20090026501A1 US11/722,208 US72220805A US2009026501A1 US 20090026501 A1 US20090026501 A1 US 20090026501A1 US 72220805 A US72220805 A US 72220805A US 2009026501 A1 US2009026501 A1 US 2009026501A1
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layer
gate
doped layer
mode transistor
semiconductor
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Hassan Maher
Pierre Baudet
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Ommic SAS
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/86—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of Schottky-barrier gate FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/84—Combinations of enhancement-mode IGFETs and depletion-mode IGFETs

Definitions

  • the invention relates to a semiconductor structure including both enhancement and depletion mode heterostructure field effect transistors (HFET), and in particular but not exclusively to a structure including high electron mobility transistors (HEMT).
  • HFET enhancement and depletion mode heterostructure field effect transistors
  • HEMT high electron mobility transistors
  • a metal gate contact forms a Schottky barrier with a Schottky barrier semiconductor layer over a channel semiconductor layer, the channel semiconductor layer forming a heterostructure with the Schottky barrier semiconductor layer.
  • Source and drain contacts are provided on either side of the gate. The voltage on the metal gate contact controls conduction in the channel between the source and drain contacts.
  • HFETs are implemented to have a high electron mobility and accordingly are known as high electron mobility transistors (HEMTs).
  • HEMTs high electron mobility transistors
  • Such HEMTs may be implemented as enhancement mode devices, which are off unless a voltage is applied to the gate to turn the device on, or depletion mode devices which are on until a voltage is applied to the gate to turn them off.
  • enhancement and depletion type FETs are known as enhancement-depletion high electron mobility transistors (ED-HEMTs), which include both enhancement and depletion HEMTs.
  • a high charge per unit area in the channel is required both to improve the intrinsic performance but also to reduce the parasitic series resistance. This is generally achieved by including a delta doped layer near the channel to provide carriers in the channel.
  • FIG. 1 illustrates such a HEMT.
  • a substrate 2 forms the base.
  • a buffer layer 4 is provided on the substrate and a channel layer 6 on the buffer layer 4 .
  • a barrier layer 8 follows and a cap layer 10 is provided on top of the substrate.
  • a delta-doped layer 16 in the barrier layer 8 provides electrons to the channel 6 .
  • the structure can produce either an enhancement or a depletion FET simply by adjusting the gate position.
  • the cap layer 10 and the barrier layer is partially etched away to create a recess in the barrier layer and a gate electrode 12 is arranged in the recess.
  • the cap layer is etched away and a gate electrode 14 arranged on the top of the barrier layer 8 .
  • the static electric field across this thin barrier can be very high, even with no gate voltage apply, which can deliver a substantial leakage current through the gate barrier reducing the maximum forward gate voltage and the gate voltage swing.
  • the series resistance of the E-HEMTs can seriously limit device performance.
  • a semiconductor structure including at least one enhancement mode transistor and at least one depletion mode transistor, the semiconductor structure comprising:
  • barrier layer of semiconductor having a second band gap higher than the first band gap on the channel layer
  • the channel layer is of semiconductor having a band gap less than the band gap of the semiconductor of the buffer layer and less than the band gap of the semiconductor of the barrier layer;
  • the at least one enhancement mode transistor includes a gate extending through the second doped layer and in contact with the barrier layer;
  • the at least one depletion mode transistor includes a gate arranged above the second doped layer.
  • the arrangement is able to reduce series resistance of the enhancement HEMT, and to deliver relatively good static and dynamic performances. Good output conductances and noise figures may be obtained, together with a wide gate voltage swing.
  • the thickness of the barrier layer between the second doped layer and the channel is preferably greater than 5 nm, further preferably greater than 10 nm.
  • the second doped layer defines an opening through the second doped layer at the enhancement mode transistor and the gate of the enhancement mode transistor extends through the opening onto the barrier layer.
  • the gate of the enhancement mode transistor includes a gate diffusion extending through the second doped layer.
  • the gate diffusion may be of platinum.
  • the gates may have a T-gate structure having a contact region in contact with second barrier layer and a region of larger lateral cross section than the contact region above the contact region.
  • the first doped layer is a delta-doped layer.
  • the second doped layer may be a delta-doped layer.
  • a spacer layer may be provided on the second doped layer.
  • a cap layer may be provided on the second doped layer, or on the spacer layer if present.
  • the cap layer may define openings for the gates of the enhancement mode transistors and for the gates of the depletion mode transistors.
  • the channel layer is of GaInAs and the buffer and barrier layers are of AlInAs. Any other appropriate material can be used.
  • a method of manufacturing a semiconductor structure including at least one enhancement mode transistor and at least one depletion mode transistor;
  • the channel layer is of semiconductor having a band gap less than the band gap of the semiconductor of the buffer layer and less than the band gap of the semiconductor of the barrier layer;
  • the at least one enhancement mode transistor depositing a gate on the barrier layer
  • the at least one depletion mode transistor depositing a gate on the second doped layer.
  • a particular benefit of the manufacturing method is that no etch stop is needed.
  • an etch stop is used to ensure that the etch to form the gates of the enhancement devices stops in exactly the correct place.
  • the pinch-off voltage is only weakly dependent on the thickness of the barrier layer under the enhancement gate So no etch stop layer is required, in other words the gates of the enhancement and depletion transistors may be placed at the same depth. So no special etch stop is needed for the enhancement transistor. Instead, either a gate diffusion or a gate extending through an opening to substantially the correct depth is used.
  • the step of forming the at least one enhancement mode transistor may includes etching a gate opening through the second doped layer and depositing the gate on the barrier layer in the opening.
  • the step of forming the at least one enhancement mode transistor may include depositing a first gate material on the second doped layer followed by diffusing the material of the first gate material through the second doped layer to the barrier layer.
  • the step of forming the gate electrodes includes depositing a diffusion gate material that diffuses through the second doped layer on the second doped layer of the enhancement mode transistor but not the depletion mode transistor;
  • the diffusion gate material may be of platinum.
  • FIG. 1 shows a conventional ED-HEMT structure.
  • FIG. 2 shows a first embodiment of an ED-HEMT structure according to the invention
  • FIG. 3 shows a second embodiment of an ED-HEMT structure according to the invention
  • FIG. 4 shows the band diagrams of the enhancement and depletion HEMTs of the first and second embodiments.
  • FIG. 5 shows a third embodiment of an ED-HEMT structure according to the invention.
  • a first embodiment of the invention starts with an InP substrate 2 .
  • An AlInAs buffer layer 4 is deposited on the substrate 2 , which in the embodiment is of Al 0.48 In 0.52 As.
  • the buffer layer is delta doped to provide a first delta-doped layer 18 near the top of the buffer layer.
  • the buffer layer is 32 nm thick and the delta doped layer is 5 nm below the top of the buffer layer.
  • the manufacture of the first delta-doped layer 18 may be carried out by any means known to those skilled in the art, including for example-interrupting the growth of the AlInAs buffer and depositing dopants.
  • a GaInAs channel layer 6 is deposited to a thickness of 10 nm, followed by a AlInAs barrier layer 8 of thickness 15 nm.
  • the composition of the AlInAs layer is again Al 0.48 In 0.52 As.
  • the AlInAs barrier layer 8 is followed by a second delta doped layer 20 .
  • This second delta doped layer is in turn is followed by an AlInAs spacer 22 approximately 5 nm thick.
  • An InGaAs cap layer 10 is provided over AlInAs spacer 22 .
  • the conduction band of the channel layer is below the conduction band of the barrier and buffer layers which is achieved through the use of a higher band gap material for the barrier and buffer layers than the channel layer.
  • An enhancement-mode HEMT 24 is provided by etching an opening 28 through the cap layer 10 and spacer layer 22 to the barrier layer 8 .
  • An enhancement HEMT gate 12 is then deposited in the opening 28 on the barrier layer 8 .
  • a depletion-mode HEMT 26 is provided by etching a opening 30 through the cap layer 10 , but not the spacer layer 22 , and depositing a depletion HEMT gate 14 in the opening 30 .
  • the gates are formed to be so-called “T-gates” shaped as a “T” where there is no contact between the foot of the crossbar of the “T” and the cap layer 10 .
  • the substrate may be InP, GaAs, etc.
  • the thickness of the buffer layer and spacer layer may be varied to achieve desired properties as will be understood by those skilled in the art.
  • the dopants may be deposited as required .
  • the channel layer may be of any suitable semiconductor material—high electron mobility materials such as InGaAs are preferred though not required.
  • the material of the barrier layer can also be varied as required.
  • FIG. 3 A second embodiment is shown in FIG. 3 which differs from the arrangement of FIG. 2 in that the second doped layer is not a delta-doped layer as in the arrangement of FIG. 2 but a thicker doped AlInAs doped layer 32 .
  • This layer means that the spacer layer 22 of the FIG. 2 arrangement is also not required.
  • the cap layer 10 is formed directly on the AlInAs doped layer 32 .
  • the opening 28 for the enhancement mode HEMT 24 passes through the cap layer 10 and the doped layer 32 , so that again the enhancement gate 12 is formed on barrier layer 8 .
  • the opening 30 for the depletion mode HEMT 26 passes through the cap layer 10 so that the gate is formed on the top of the doped layer 32 .
  • FIG. 4 shows the band diagram of the three structures under the respective cap layer, with 0.00 ⁇ m being defined as the position under the cap layer, i.e. for a depletion mode HEMT at the interface between the gate and the underlying layer.
  • a depletion mode HEMT For an enhancement mode HEMT, for which the gate is lower in the via, the HEMT starts 5 nm lower and there is no data for the range 0 to 5 nm which is in the HEMT.
  • the enhancement mode HEMT is shown in dashed lines
  • the depletion mode HEMT of the second embodiment is shown in dotted line
  • the depletion mode HEMT of the first embodiment is shown in dotted-dashed lines.
  • the enhancement mode HEMT does not have any of the conduction band of the channel layer below the Fermi level 34 and so is an enhancement mode HEMT which needs an applied gate voltage to turn on.
  • both the depletion mode HEMT band diagrams do have the channel layer conduction band below the Fermi level 34 and so represent normally-on depletion mode transistors.
  • a benefit of these embodiments is that the depth of the gate opening 28 for the enhancement mode HEMT 24 does not have to be precisely controlled, since the pinch off voltage is almost independent of the barrier layer 8 thickness. This means that the barrier layer 8 does not need to act as a good etch stop which allows for a greatly improved series resistance and correspondingly good dynamic performance of an E-HEMT which has been very difficult if not impossible to achieve previously in ED-HEMTs.
  • the selectivity in etch rates between InGaAs and InAlAs is about 20. This would not be sufficient for prior art arrangements but is acceptable in the present approach so no additional etch stop layer needs to be added.
  • FIG. 5 A further embodiment is shown in FIG. 5 .
  • This uses a doped layer 32 as in the second embodiment, though it could be adapted to use instead a delta doped layer as in the first embodiment.
  • an opening 30 to the same depth is provided in the cap layer 10 in both the enhancement and depletion mode HEMTs 24 , 26 .
  • a gate electrode is deposited. The material of the gate electrode is different for the enhancement and depletion mode HEMTs.
  • the gate material 40 is a relatively conventional Titanium/Platinum/Gold multilayer 42 .
  • a diffusion layer of platinum 44 is provided on the barrier layer 20 followed by the same Titanium/Platinum/Gold multilayer 42 as for the depletion mode HEMT.
  • a diffusion process is carried out in the baking step, which is included in any event in the process, which diffuses platinum through the barrier layer 20 so that the platinum forms a diffused gate 46 is in contact with the doped layer . . . .
  • the depth of the diffused gate can be controlled by varying the thickness of the diffusion layer of platinum.
  • the buried enhancement gate is readily manufactured since there is no need for a precisely controlled etching of the doped layer 32 in the enhancement mode FET.
  • the invention allows a barrier layer thickness above 5 nm, for example 10 nm or more.
  • the invention thus permits the fabrication of an ED-HEMT having good static and dynamic performance, a low series resistance and an improved output conductance.
  • the noise performance is improved even at relatively low frequency due to a relatively low leakage current and the effective barrier height is good leading to a wide allowable gate voltage swing for the E-HEMT.
  • the D-HEMT gives similar performance in terms of the dynamic performances to conventional D-mode HEMTS in ED-HEMT structures but a significant improvement in maximum frequency because of the lower output conductance.

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EP04300956 2004-12-30
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EP (1) EP1834360A2 (de)
JP (1) JP2008527687A (de)
KR (1) KR20070093074A (de)
CN (1) CN101095233A (de)
TW (1) TWI415259B (de)
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US20110147845A1 (en) * 2009-12-22 2011-06-23 Prashant Majhi Remote Doped High Performance Transistor Having Improved Subthreshold Characteristics
US20130307091A1 (en) * 2011-04-08 2013-11-21 Infineon Technologies Ag Schottky Diodes Having Metal Gate Electrodes and Methods of Formation Thereof
US9083334B2 (en) 2008-10-31 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Logic circuit
US9679975B2 (en) 2014-11-17 2017-06-13 Samsung Electronics Co., Ltd. Semiconductor devices including field effect transistors and methods of forming the same
US20170340449A1 (en) * 2014-12-10 2017-11-30 Tornier Sas Convertible stem / fracture stem
US10170610B1 (en) * 2018-03-16 2019-01-01 Qualcomm Incorporated Pseudomorphic high electron mobility transistor with low contact resistance
WO2019160598A1 (en) * 2018-02-14 2019-08-22 Hrl Laboratories, Llc HIGHLY SCALED LINEAR GaN HEMT STRUCTURES
TWI692875B (zh) * 2019-02-04 2020-05-01 穩懋半導體股份有限公司 增強型及空乏型場效電晶體之單晶集成
US10734498B1 (en) 2017-10-12 2020-08-04 Hrl Laboratories, Llc Method of making a dual-gate HEMT
US11081355B2 (en) * 2019-08-07 2021-08-03 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing same
US11404541B2 (en) 2018-02-14 2022-08-02 Hrl Laboratories, Llc Binary III-nitride 3DEG heterostructure HEMT with graded channel for high linearity and high power applications
US20230080772A1 (en) * 2021-09-13 2023-03-16 Walter Tony WOHLMUTH Field effect transistor

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US20080001173A1 (en) 2006-06-23 2008-01-03 International Business Machines Corporation BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS
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US20100148153A1 (en) * 2008-12-16 2010-06-17 Hudait Mantu K Group III-V devices with delta-doped layer under channel region
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US9087718B2 (en) 2013-03-13 2015-07-21 Transphorm Inc. Enhancement-mode III-nitride devices
US9502535B2 (en) * 2015-04-10 2016-11-22 Cambridge Electronics, Inc. Semiconductor structure and etch technique for monolithic integration of III-N transistors
US10529561B2 (en) * 2015-12-28 2020-01-07 Texas Instruments Incorporated Method of fabricating non-etch gas cooled epitaxial stack for group IIIA-N devices
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US9083334B2 (en) 2008-10-31 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Logic circuit
US20130105910A1 (en) * 2009-12-22 2013-05-02 International Sematech Remote Doped High Performance Transistor Having Improved Subthreshold Characteristics
US20110147845A1 (en) * 2009-12-22 2011-06-23 Prashant Majhi Remote Doped High Performance Transistor Having Improved Subthreshold Characteristics
US20130307091A1 (en) * 2011-04-08 2013-11-21 Infineon Technologies Ag Schottky Diodes Having Metal Gate Electrodes and Methods of Formation Thereof
US8901624B2 (en) * 2011-04-08 2014-12-02 Infineon Technologies Ag Schottky diodes having metal gate electrodes and methods of formation thereof
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CN101095233A (zh) 2007-12-26
KR20070093074A (ko) 2007-09-17
WO2006070297A2 (en) 2006-07-06
TW200636997A (en) 2006-10-16
EP1834360A2 (de) 2007-09-19
TWI415259B (zh) 2013-11-11
WO2006070297A3 (en) 2006-10-05
JP2008527687A (ja) 2008-07-24

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