US4467419A - Data processing system with access to a buffer store during data block transfers - Google Patents

Data processing system with access to a buffer store during data block transfers Download PDF

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US4467419A
US4467419A US06/331,895 US33189581A US4467419A US 4467419 A US4467419 A US 4467419A US 33189581 A US33189581 A US 33189581A US 4467419 A US4467419 A US 4467419A
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data
access request
buffer storage
access
address
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US06/331,895
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English (en)
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Katsuro Wakai
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Hitachi Ltd
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Hitachi Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the present invention relates to a data processing system, and more particularly to a data processing system having a buffer storage.
  • a large scale data processing system comprises a main storage (MS) 20 for storing data (instructions and operands) and a central processing unit (CPU) 10 which includes a basic processing unit (BPU) 11 for executing the instructions, a buffer storage (BS) 12 for storing a partial copy of the MS 20, an input/output processor (IOP) 13 for controlling data transfer between an input/output unit (IO) and the MS 20 and a storage control unit (SCU) 14 for controlling read and write operations of the MS 20 and the BS 12.
  • MS main storage
  • CPU central processing unit
  • CPU central processing unit
  • BPU basic processing unit
  • BS buffer storage
  • IOP input/output processor
  • SCU storage control unit
  • a difference in the configuration of FIG. 1 from small and middle scale information processing systems resides in the fact that the buffer storage 12 is provided and the storage control unit 14 is an independent unit which executes and controls or buffers accesses to the MS 20 and the BS 12 when such accesses ae requested simultaneously so that the data transfer ability of the system is considerably increased.
  • the BS 12 is a small capacity, high speed memory unit.
  • the content of the MS 20 is divided into a plurality of sequential multi-byte (e.g. 64 bytes) blocks.
  • the BS 12 stores a copy of the content of the MS 20 in the unit of a block.
  • the instructions are pipeline-controlled so that the execution of an instruction which spreads over a number of cycles is accomplished at a rate of one instruction per cycle.
  • FIG. 2 shows a sequence chart for a conventional control system as a whole.
  • FIG. 2(a) shows the status of the BS 12 and FIG. 2(b) shows the pipeline control stages of the instruction.
  • the stage D is a decode stage which is carried out independently and in which an instruction is fetched from an instruction fetch control unit which supplies an instruction word and the fetched instruction is decoded.
  • the stage A is an address translation stage in which a virtual address of an operand read request is translated to a real address and the registration of an area corresponding to the translated real address in the BS 12 is checked.
  • the stage L is a data read stage in which an operand read request is issued to the BS 12 and the read operand is transferred to an arithmetic unit of the BPU 11.
  • the stage E is an instruction execution stage in which the operand read by the arithmetic unit of the BPU 11 is processed, the result is checked and a store request of the result is issued to the BS 12 and the MS 20 or the result is loaded to a general purpose register or a floating point register.
  • each of the stages D through E can be completed in one cycle and the instructions can be sequentially executed. Accordingly, each instruction can be effectively executed in one cycle.
  • the symbol i indicates an initiation time of the execution in the respective pipeline control stages.
  • the position of the symbol i shows the transition of the machine cycle time in the BPU 11 and the instruction execution status for the stages D through E.
  • FIG. 2(a) shows the status of the BS 12, that is, AV (available), CL (close) and WT (write).
  • the BS 12 can accept the access request from the BPU 11.
  • the access request from the BPU 11 is not accepted during the block transfer from the MS 20 because the access request was issued from the BPU 11 to the BS 12 but the corresponding data was not in the BS and the block transfer request has been issued to the MS 20.
  • the access request from the BPU 11 is not accepted because the block data tansferred from the MS 20 is being written to the BS 12.
  • the instruction or operand is transferred from the SCU 14 to the BPU 11 sixteen bytes at a time.
  • a read termination signal is sent to the BPU 11 and the data is transferred.
  • the instruction 2 shown in FIG. 2(b) waits for the termination of the operand read at the stage L, and at the third cycle from the beginning of the status WT, it can shift to the stage E.
  • the instruction 3 which instructs the readout from the BS 12, however, is not completed in the status WT because the write status WT to the BS 12 due to the block transfer by the instruction 2 continues for eight cycles and it has to wait for six cycles in the stage L.
  • the operand readout is completed when the status of the BS 12 shifts from WT to AV and the instruction 3 can shift to the stage E.
  • the processing performance may be increased.
  • the semiconductor devices used in the BS 12 must be of high performance, they are integrated in a low density, consume large power, are very expensive and must operate at a high speed. Accordingly, it is practically difficult to increase the capacity of the BS 12.
  • BPU basic processing unit
  • the present invention provides a data processing system having a main storage (MS) and a buffer storage (BS) and a control unit which controls the read and write operations of the MS and the BS.
  • the MS is divided into blocks each containing a plurality of data bytes and the MS stores a number of data.
  • the BS stores a copy of one of the blocks of the MS.
  • the MS transfers a block of data to the control unit in several units at successive times each together with a first access request in order to write the block of data into the BS.
  • the BPU issues a second access request to the control unit to read or write the data from or into the BS.
  • the control unit accepts the second access request between the sequential first access requests.
  • FIG. 1 shows a block diagram of a conventional data processing system
  • FIG. 2 shows a sequence chart for explaining the operation of the conventional data processing system
  • FIG. 3 shows a sequence chart for explaining a principle of the present invention
  • FIG. 4 shows a block diagram of one embodiment of the present invention
  • FIGS. 5a and 5b illustrate sequences of transferred data to a BS shown in FIG. 4,
  • FIG. 6 shows a detail of an address control circuit shown in FIG. 4,
  • FIG. 7 shows an access request selective accept circuit.
  • FIG. 3 illustrates a principle of the present invention, and shows the status of the BS and the execution status of the instruction for each pipeline control stage when the same instruction as that of FIG. 2 is executed.
  • the configuration of the data transfer path from the MS 20 to the BS 12 is the block transfer is modified and the priority of the BPU access request and the block transfer request is controlled.
  • the unit of data capable of being written into the BS 12 from the MS 20 is a plural number of times as large as that of the conventional system, that is, a plural number of times (for example, two times) as large as the data transfer width so that the block transferred data is written sixteen bytes at a time.
  • the status WT in FIG. 3(a) the status AV which allows the acceptance of the BPU access request is established only for one cycle between the write cycle and the following write cycle. Consequently, following to the execution of the instruction 2 which instructs the initiation of the block transfer, the operand for the instruction 3 and the operands for the instruction 4 and 5 can be read so that the overall processing performance is improved.
  • a probability of non-registration of the access request from the BPU 11 in the BS 12 is usually no less than 10% per instruction in the large program system although it depends on a particular program.
  • an effective overhead of the block transfer is equal to a product of the overhead of the block transfer (14 cycles) times the probability (10%), that is, 1.4 cycles per instruction.
  • the effective overhead is equal to a product of 17 cycles times 10%, that is, 1.7 cycles. Accordingly, the present invention can increase the processing speed by 0.3 cycle per instruction. Since one instruction is executed in four cycles on the average, the processing performance is improved by approximately 8% in the present invention.
  • FIG. 4 shows a block diagram of BS's and peripheral circuits in one embodiment of the present invention.
  • a bank A of a BS 42 and a bank B of a BS 43 can read and write eight-byte (doubleword) data and can be independently accessed by addresses loaded in a register 33 and a register 34, respectively.
  • a doubleword of data to be stored in the bank A 42 is loaded in a register 40, and a doubleword of data to be stored in the bank B 43 is loaded in a register 41.
  • the doublewords of data read from the bank A 42 and the bank B 43 are loaded to registers 44 and 45, respectively.
  • the addressing to the bank A 42 and the bank B 43 is done alternately in units of eight bytes.
  • addresses 0-7 are allotted to the bank A 42
  • the following addresses 8-15 are allotted to the bank B 43
  • the addresses 16-23 are allotted to the bank A 42
  • the addresses 24-31 are allotted to the bank B 43 and so on.
  • the eight bytes at the corresponding address 0-7 are parallelly read from the bank A 42 and loaded into the register 44.
  • the address is supplied to a multiplexor (MPX) 31 through a path 46 and the store data is supplied to a multiplexor (MPX) 38 or 39 through a path 48.
  • MPX multiplexor
  • the address is supplied to the multiplexor (MPX) 31 through a path 47 and the block data is supplied to registers (REG) 36 and 37 through a path 49.
  • the block transfer request from the MS and the access request from the BPU are selectively accepted and the address supplied through the path 46 or 47 is selected by the multiplexor 31 and supplied to an address register (AR) 32.
  • AR address register
  • the acceptance of the access request will be explained later in connection with FIG. 7.
  • the content of the address register 32 is supplied to the two registers 33 and 34 with portions of the address bits being supplied to the register 33 through an address control circuit 35.
  • the address control circuit 35 will be explained later in conjunction with FIG. 6.
  • the address bits supplied to register 33 are not modified by the address central circuit 35 when a 2 3 -bit of the address in the register 32 is "0" (that is, when the doubleword address excluding the three low order bits of the address is even), but eight is added to the address by the address control circuit 35 when the 2 3 bit is "1" (that is, when the doubleword address excluding the three low order bits of the address is odd), as will be described in more detail hereinafter.
  • the write data is sent from the BPU, eight bytes at a time, through the path 48, either one of the multiplexors 38 or 39 is selected and the content thereof is loaded into the register 40 or 41 and thence written into the BS 42 or 43.
  • the write address is an even doubleword address
  • the multiplexor 38 and the register 40 are selected and the data is written at the address specified by the address register 33
  • the write address is an odd doubleword address
  • the multiplexor 31 and the register 41 are selected and the data is written at the address specified by the address register 34.
  • the block transfer data is sent from the MS through the path 49 in eight cycles, 8 bytes in each cycle.
  • the block transfer from the MS to the BS is accomplished first to the address requested by the block transfer request and then to incremental interblock addresses.
  • the three-bit address is sequentially incremented from "000" to "111" to effect the block transfer. When the address reaches "111", it is wrapped around to "000".
  • the even bank 42 and the odd bank 43 of the BS are paired, and when the block transfer is to start from an odd doubleword address, the odd bank and the even bank 42 are paired.
  • FIGS. 5a and 5b illustrate the write sequence of the block transferred data to the BS shown in FIG. 4.
  • FIG. 5a illustrates in decimal notation
  • FIG. 5b illustrates in binary rotation.
  • the data at the interblock high order address "000” is stored at the addresses 0-7 in the odd bank 42
  • the data at the interblock high order address "001” is stored at the address 8-15 in the odd bank 43
  • the data at the interblock high order address "010” is stored at the addresses 16-23 in the even bank 42 and so on.
  • the addresses 0-7 of the even bank 42 and the addresses 8-15 of the odd bank 43 are paired so that sixteen bytes are parallelly written in the BS (as shown by hatched areas). If the block transfer starts from the odd doubleword address, for example "101”, the addresses 40-47 of the odd bank 43 and the addresses 48-55 of the even bank 42 are paired so that sixteen bytes are parallelly written in the BS (as shown by hatched areas).
  • the write address for the even bank 42 of the BS is larger than that of the odd bank 43 by eight (or one as viewed from the interblock high order address).
  • FIG. 5b which shows the interblock high order address in binary notation
  • the address control circuit 35 controls the addressing.
  • the address control circuit 35 checks the fourth bit (2 3 bit) in the interblock address counted from the least significant bit to determine if it is "1" or "0", and if it is "0", the interblock address is loaded into the register 33, and if it is "1", the interblock address is incremented by eight and the incremented address is loaded into the register 33.
  • the address to be loaded into the register 33 need not be modified because the even bank 42 and the odd bank 43 are paired, and if it is odd, the address incremented by eight by the address control circuit 35 is loaded into the register 33 because the even bank 42 which is one row lower than the odd bank 43 is used to write the data.
  • FIG. 6 shows a logic circuit for the address modification in the address control circuit 35 of FIG. 4.
  • the address control circuit 35 modifies two high order bits of the interblock high order address.
  • AR (3, 2) indicates a second bit of a third byte of the address, AND denotes an AND gate and OR denotes an OR gate.
  • AR (3, 2), AR (3, 3) and AR (3, 4) which are the interblock high order address of the output from the address register 32 shown in FIG. 4 are supplied to the logic circuit of FIG. 6, which produces output data RGIN (3, 2) and RGIN (3, 3) to the register 33 for the memory bank of the BS.
  • AR (3, 2), AR (3, 3), AR (3, 4) and RGIN (3, 2), RGIN (3, 3) is shown below.
  • AR (3, 4) or the 2 3 bit is "0"
  • AR (3, 2) and AR (3, 3) appear as RGIN (3, 2) and RGIN (3, 3) without modification, and when it is "1", they are incremented by eight.
  • the interblock high order address is "001" and the data requested by the access request from the BPU has not been registered in the BS
  • a block transfer from the MS starts.
  • the access to the MS has been accepted and the data is sequentially transferred from the MS to the BS
  • the first data at the interblock high order address "001" is first loaded into the register 37 through the path 49.
  • the address circuit and the BS are not affected at this time.
  • the second data at the next interblock high order address "010" is sent through the path 49 and loaded into the register 36.
  • the address is simultaneously supplied through the path 47.
  • the SCU preferentially handles the block transfer request so that the path 47 is selected by the multiplexor 31 and the address is loaded into the register 32.
  • the contents of the registers 37 and 36 are loaded into the registers 41 and 40, respectively, through the multiplexors 39 and 38, and are also loaded into the registers 45 and 44, respectively.
  • the registers 41 and 40 retain the data to be written in the banks 43 and 42 of the BS, respectively, and the registers 45 and 44 retain the read data to be transferred to the BPU.
  • the address in the register 32 is loaded directly into the register 34, while the address increased by eight by the address control circuit 35 is loaded into the register 33.
  • the addresses are supplied to the banks 43 and 42 of the BS and a write pulse is simultaneously applied thereto, the 8-byte (doubleword) data in the register 41 is written in the bank 43 and the 8-byte data in the register 40 is written in the bank 42.
  • the contents of the registers 45 and 44 are fed to the BPU as the instruction or the operand.
  • the data at the interblock high order address "011" is supplied to the register 37 through the path 49.
  • the address circuit, the BS and the registers 44 and 45 are used to handle the access request from the BPU.
  • the multiplexor 31 selects the path 46 and the multiplexors 38 and 39 select the path 48.
  • the data at the interblock high order address "100" is transferred to the register 36.
  • the data is then written in the banks 43 and 42 in the same manner as above.
  • the access request from the BPU to the BS is inhibited.
  • the data at the interblock high order address "101" is transferred from the MS 20.
  • the multiplexors 31, 38 and 39 select the paths 46 and 48 to accept the access request from the BPU.
  • the block transfer of the data at the interblock high order address "110" is accepted and the data at the interblock high order addresses "101" and "110" are written in the BS.
  • the registers 36 and 37 buffer data of two block transfers.
  • FIG. 7 shows an example of an access request selective accept circuit.
  • a logic circuit shown in FIG. 7 is used to selectively accept the block transfer request from the MS and the access request from the BPU.
  • the block transfer request from the MS is supplied to a counter 81 through a path 72.
  • the counter 81 counts two access requests, it produces a "1" output which is fed to a data input terminal D of a flip-flop 84.
  • This signal is sampled when a clock supplied through a path 71 is “1" to produce a "1" output on a path 78. Accordingly, for every two access requests transferred from the MS, one access request is accepted.
  • the signal on the path 78 selects the multiplexors 31, 38 and 39 to the MS.
  • a flip-flop 83 indicates the status CL shown in FIG. 3. It is set by a signal on a path 75 which is present when the data requested by the BPU is not in the BS and the block transfer is requested to the MS, and reset by the initiation of the block transfer.
  • the reset output of the flip-flop 83 is supplied to an AND gate 82 through a path 77.
  • the access request from the BPU is supplied to the AND gate 82 through a path 73.
  • the AND gate 82 is opened to set a flip-flop 85 to produce a "1" output on a path 79 so that the access request from the BPU is accepted.
  • the signal on the path 79 selects the multiplexors 31, 38 and 39 to the BPU.
  • the eight-byte registers 36 and 37 are used to buffer sixteen-byte data transferred in two cycles from the MS, and write the sixteen-byte data in the BS in one access cycle.
  • 8n-byte data transferred in n cycles may be buffered and the 8n-byte data may be written in the BS in one access cycle.
  • the present invention is not limited to the specific embodiment and the byte width may be variable.

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US06/331,895 1980-12-23 1981-12-17 Data processing system with access to a buffer store during data block transfers Expired - Fee Related US4467419A (en)

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JP55-182543 1980-12-23
JP55182543A JPS57105879A (en) 1980-12-23 1980-12-23 Control system for storage device

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Publication number Publication date
DE3176548D1 (en) 1988-01-07
EP0054888B1 (fr) 1987-11-25
EP0054888A3 (en) 1984-07-04
EP0054888A2 (fr) 1982-06-30
JPS57105879A (en) 1982-07-01

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