US4947342A - Graphic processing system for displaying characters and pictures at high speed - Google Patents

Graphic processing system for displaying characters and pictures at high speed Download PDF

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Publication number
US4947342A
US4947342A US06/905,173 US90517386A US4947342A US 4947342 A US4947342 A US 4947342A US 90517386 A US90517386 A US 90517386A US 4947342 A US4947342 A US 4947342A
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Prior art keywords
information
pixels
character font
states
output
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US06/905,173
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Inventor
Koyo Katsura
Shigeru Matsuo
Shigeaki Yoshida
Hiroshi Takeda
Hisashi Kaziwara
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Hitachi Ltd
Hitachi Industry and Control Solutions Co Ltd
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Hitachi Engineering Co Ltd Ibaraki
Hitachi Ltd
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Assigned to HITACHI, LTD., A CORP OF JAPAN, HITACHI ENGINEERING CO., LTD. reassignment HITACHI, LTD., A CORP OF JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: KATSURA, KOYO, KAZIWARA, HISASHI, MATSUO, SHIGERU, TAKEDA, HIROSHI, YOSHIDA, SHIGEAKI
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Priority to US08/213,820 priority Critical patent/US5751930A/en
Priority to US08/625,241 priority patent/US6538653B1/en
Priority to US09/454,590 priority patent/US6697070B1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns
    • G09G5/26—Generation of individual character patterns for modifying the character dimensions, e.g. double width, double height
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Definitions

  • This invention relates to graphic processing systems for delivery of character outputs to be displayed or printed and more particularly to a graphic processing system for storage and delivery of characters in the form of pixel unit information and is suitable for high speed processing when developing characters at given positions.
  • bit map memory a memory adapted to store information corresponding to each pixel of a display unit.
  • This system adopting the bit map memory has also been used to control output signals to a printer.
  • a procedure to issue character and graphic data to the bit map memory has mainly relied upon software which handles a great amount of data, raising a problem of low processing speed.
  • hardware is dedicated thereto in some applications but is problematically expensive.
  • This LSI implementation permits a remarkable increase in speed of graphic processing at relatively low costs.
  • the LSI implementation also has a function of copying and transferring information in a rectangular region at high speeds, which function may be applied to a character display. Details of the copying function are proposed by the present inventors in U.S. patent application Ser. Nos. 686,039 filed Dec. 24, 1984 and 727,850 filed Apr. 26, 1985.
  • the system applying the copying function to the bit map character display can afford to greatly promote the processing speed as compared to the prior art system based on software. For example, where 1000 Chinese characters each composed of 24 dots ⁇ 24 dots are displayed in the monochromatic mode, the entire screen can be renewed within about 0.5 to 1 second.
  • An object of this invention is to provide a graphic processing system capable of realizing high speed development of fonts in order to speed up bit map character display.
  • the present invention provides a processor for managing a display area and a character font area which are included within an address space, and the processor calculates, from coded information indicative of a character transferred through a data bus of a system, an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area.
  • character is the concept representative of the fundamental unit of graphic information such as "English letters”, “numerals”, “Chinese letters”, “kana letters”, “symbols” and "fundamental graphics”.
  • FIG. 1 is a block diagram showing the construction of a graphic processing system according to an embodiment of the invention
  • FIG. 2 is a block diagram showing the internal construction of a graphic drawing processor
  • FIG. 3 is a diagram illustrative of a terminal layout of the graphic drawing processor
  • FIGS. 4 to 6 explain internal registers of the graphic drawing processor
  • FIG. 7 is a diagram useful in explaining a put image data (PUT) command
  • FIG. 8 is a similar diagram for a get image data (GET) command
  • FIG. 9 diagrammatically explains an elliptic arc (ELARC) command
  • FIGS. 10 and 11 diagrammatically explain filled elliptic fan (FEFAN) commands
  • FIG. 12 diagrammatically explains a filled triangle (FTRI) command
  • FIG. 13 is a diagram for explaining zoom (ZOOM) commands
  • FIGS. 14 and 15 are diagrams for explaining a rotation (ROT) command
  • FIGS. 16 and 17 are diagrams for explaining a text (TEXT) command
  • FIG. 18 is a diagram for explaining a text with proportional spacing (TEXTPS) command
  • FIG. 19 is a schematic block diagram showing a system for character font development
  • FIGS. 20 and 21 explain an absolute pointer move (APMV) command
  • FIGS. 22 and 23 explain a relative pointer move (RPMV) command
  • FIGS. 24 and 25 explain a search (SRCH) command
  • FIG. 26 is a diagram for explaining a test dot (TDOT) command
  • FIGS. 27 (A) and (B) explain a copy (COPY) command
  • FIG. 28 is a diagrammatic representation illustrative of a transfer model based on the copy command
  • FIG. 29 is a schematic block diagram showing another embodiment of the invention.
  • FIG. 30 is a block diagram showing the internal construction of a graphic memory interface controller GMIC
  • FIG. 31 is a diagram illustrative of a terminal layout of the CMIC.
  • FIG. 32 is a block diagram showing the internal construction of a graphic video attribute controller (GVAC);
  • GVAC graphic video attribute controller
  • FIG. 33 is a diagram illustrative of a terminal layout of the GVAC.
  • FIGS. 34, and 34(A)-34(C) are views showing a layout in which FIGS. 34(A), 34(B) and 34(C) are to be arrayed, wherein FIGS. 34(A), 34(B) and 34(C) combined together as shown in FIG. 34 show in detail a circuit diagram of the graphic display system according to an embodiment of the invention.
  • FIG. 1 schematically showing the entire construction of a graphic processing system according to a preferred embodiment of the invention.
  • the graphic processing system comprises a graphic data processor (GDP) 10, a central processing unit (CPU) 11, a main memory 12, a direct memory access controller (DMAC) 13, a frame buffer 14, a parallel-serial converter 15, a display unit (CRT) 16 which is an output device, a multiplexer 17, and a latch 18.
  • GDP graphic data processor
  • CPU central processing unit
  • DMAC direct memory access controller
  • CRT display unit
  • the CPU 11 executes and processes programs stored in the main memory 12 to manage and control the complete system.
  • the DMAC 13 controls direct memory access between the main memory 12 and the GDP 10 or between the main memory 12 and another input/output unit such as a printer (not shown).
  • the GDP 10 receives a command and parameter information transferred from the CPU 11 or main memory 12 and accesses the frame buffer 14 in accordance with a predetermined processing procedure to generate and transfer characters and graphic data.
  • the GDP 10 also plays the part of generating a sync timing signal which controls the display unit 16 and of controlling read-out of information to be sequentially displayed from the frame buffer 14 in synchronism with a given timing.
  • Display data read out of the frame buffer 14 in parallel is converted by the parallel-serial converter 15 into a high speed serial signal and sent to the display unit 16 of, for example, a CRT, liquid crystal, EL or ECD so as to be displayed on its screen.
  • the multiplexer 17 switches the supply of an address to the frame buffer 14 so that the address is fed from either an address bus connected to the GDP 10 or an address bus connected to the CPU 11.
  • the latch 18 is adapted to fetch only address information from composite information of address and data.
  • the frame buffer 14 is configured to include both a display area, serving as a first area, for storing data corresponding to individual pixels within at least one screen of the display unit and a character font area, serving as a second area, for storing character font data for at least one screen.
  • the GDP 10 includes registers for storing the font area start address (FSAH, FSAL) and a register for storing the total number of bits (FBN) constituting one character, so that with a parameter transferred from the CPU 11 or main memory 12 through a data bus of the system, an address at which a corresponding character pattern is stored can be generated by designating a particular number to each coded character. This function permits speed-up of character processing as will be detailed below.
  • FIG. 2 shows the internal construction of the GDP 10.
  • the GDP 10 comprises a drawing processor 101, a display processor 102, a timing processor 103, a CPU interface 106, an interruption controller 105, a direct memory access (DMA) control circuit 104, a display interface 108, and a bus controller 107.
  • the drawing processor 101 adapted to control generation of graphics such as line and plane and data transfer between the CPU 11 and the display area corresponding to the frame buffer 14, delivers out a drawing address for read/write of the display area 14.
  • the display processor 102 delivers out display addresses of the display area of frame buffer 14 data which are sequentially displayed in accordance with raster scanning.
  • the timing processor 103 generates various timing signals such as a sync signal and a display timing signal for the CRT 16 as well as a signal for switching display and drawing.
  • the CPU interface 106 serves for interface between the CPU 11 and GDP 10 such as synchronization between a CPU data bus and the GDP 10.
  • the interruption controller 105 generates an interruption request signal (IRQ) to the CPU 11.
  • the DMA control circuit 104 controls exchange of control signals between the DMAC 13 and the circuit 104.
  • the display interface 108 serves for interface between the frame buffer 14 and display unit such as control of switching between display and drawing addresses.
  • the bus controller 107 controls the accessing of a bus for the frame buffer 14, and also controls access to the bus based on an external request signal.
  • three processors, that is, the drawing, display and timing processors each have a distributed function and operate in parallel to improve processing efficiency.
  • FIG. 3 shows a layout of terminals of the GDP 10 shown in FIG. 2. Individual terminals function as follows.
  • Terminals Vss are grounded and terminals Vcc are applied with +5V.
  • the D0 to D15 signals are input/output signals used for data transfer between a processing system including the CPU 11 and the GDP 10. Selection between 8-bit interface and 16-bit interface is permissible to comply with the data bus width of the processing system.
  • the R/W signal is an input signal for controlling the direction of data transfer between the processing system including the CPU 11 and the GDP 10.
  • the R/W signal When the R/W signal is at a "High” level, the data transfer is directed from GDP 10 to CPU 11 and when the R/W signal is at a "Low” level, the data transfer is directed from CPU 11 to GDP 10.
  • DMA transfer In DMA transfer, however, transfer is from main memory 12 to GDP 10 when the R/W signal is high and from GDP 10 to main memory 12 when the R/W signal is low.
  • the CS signal is an input signal which the CPU 11 uses to access the GDP 10. With the CS signal being at "Low”, read/write of the internal registers of the GDP 10 is permitted to execute.
  • the RS signal is an input signal for selection of the internal registers of the GDP 10.
  • the address register is selected with the R/W signal being at the "Low” level whereas the status register is selected with the R/W signal being at the "High” level.
  • a control register designated by the address register is selected.
  • the DTACK signal is an output signal indicative of completion of the data transfer and used as a transfer control signal in asynchronous bus interface.
  • the RES signal is an input signal for resetting the internal status of the GDP 10.
  • SR status register
  • OMR operation mode register
  • CCR command control register
  • the IRQ signal is an output signal for informing the CPU of ending of a command processing and detection of an undefined command.
  • the DREQ signal is an output signal for sending a data transfer request to the DMAC 13 when executing data transfer in the DMA transfer mode.
  • the DREQ signal is generated by executing a DMA transfer command or by setting a DMA transfer mode bit (CDM) of the command control register to "1".
  • CDM DMA transfer mode bit
  • DMA transfer mode either one of two modes, a cycle steal mode and a burst mode, can be selected by setting a DMA transfer request control bit (DRC) of the command control register.
  • the DACK signal is an input signal from the DMAC 13 responsive to the DREQ signal.
  • the DACK signal is at the "Low” level, the GDPAO recognizes the R/W signal being in opposite polarity with respect to usual access.
  • the DACK signal is also used to set the interface mode of the data bus after resetting into the GDP 10. If the DACK is high when the RES signal rises from low to high, the 16-bit interface is set and thereafter the D0 to D15 signals are used for data transfer between the GDP 10 and the CPU 11. If the DACK signal is low, the 8-bit interface is set and thereafter only the D0 to D7 signals are used and the signals D8 to D15 are made invalid. In the 16-bit interface mode, the automatic increment mode of the address register becomes +2 increment (only even addresses) and in the 8-bit interface mode, it becomes +1 increment.
  • the DONE signal is an input/output signal indicative of end of the DMA transfer.
  • the DONE signal becomes an output signal and becomes the "Low" level at the termination of the DMA transfer.
  • the DONE signal becomes an input signal for reception of a data transfer termination signal from the DMAC 13.
  • the CLK signal is a clock input signal to which the internal operation of the GDP 10 is referenced.
  • the CLK signal has a frequency which is n times (n being programmable ) the memory access timing frequency (memory cycle) and is fed from an external high speed dot timing circuit.
  • the VSYNC signal is an output signal for applying vertical synchronization to the CRT display unit 16.
  • the HSYNC signal is an output signal for applying horizontal synchronization to the CRT display unit 16.
  • a start bit (STR), mentioned hereinafter, to be described later is set to "0" or a RAM mode bit (RAM), mentioned hereinafter, to be described later is set to "0" in the operation mode register
  • the HSYNC signal becomes an output signal indicating that terminals for memory address/data (MAD), mentioned hereinafter, to be described later output a refresh address.
  • the EXSYNC signal is an input/output signal for parallel operations of a plurality of GDP's 10 or a synchronous operation of an external apparatus such as another CRT controller or a video device and the GDP 10.
  • the GDP 10 is used as a master device which supplies a reference signal for the synchronous operation (when a master/slave bit (M/S), mentioned hereinafter, to be described later of the operation mode register is "1"
  • M/S master/slave bit
  • the EXSYNC signal becomes an output signal.
  • the VSYNC signal is branched and used as the EXSYNC output signal.
  • the VSYNC signal for odd fields is branched and used as the EXSYNC output signal.
  • the EXSYNC signal becomes an input signal.
  • the VSYNC signal is branched and used as the EXSYNC input signal for synchronous operation.
  • the VSYNC signal for odd fields is branched and used as the EXSYNC input signal for synchronous operation.
  • the MCYC signal is an output signal indicative of an access timing for the frame buffer of the GDP 10.
  • the MCYC signal becomes low when the GDP 10 is in the address cycle and becomes high when the GDP 10 is in the data cycle.
  • the AS signal is an output signal of latch timing for a display memory address When the AS signal is at the "Low” level, an address can be separated by latching the output signal of the MAD15 - MAD0 terminal.
  • the AS signal is also used as a selection signal for loading data read out of the frame buffer 14 during the display cycle period to the parallel-serial converter (shift register) 15.
  • the MRD signal is an output signal for controlling the direction of data transfer between the GDP 10 and the display memory. Specifically, when the MRD signal is high, the frame buffer 14 is read by the GDP 10 and when low, the frame buffer 14 is written.
  • the DRAW signal is an output signal to indicate whether the GDP 10 is in the drawing cycle or in the display cycle.
  • the DRAW signal is low, the GDP 10 is placed in the drawing cycle, and the MAD15 - MAD0 signal becomes a multiplexed signal of a drawing address and a drawing data.
  • the DRAW signal is high, the GDP 10 is placed in the display cycle and the MAD terminal delivers a display address during the address cycle period.
  • the MAD signal is a multiplexed input/output signal consisting of an address (lower 16 bits) of the frame buffer 14 and a data (16 bits).
  • the MAD terminal delivers the address.
  • the MAD terminal becomes a bidirectional data bus of 16 bits for input/output of the drawing data.
  • the RAM bit of the operation mode register is set with "0"
  • the MAD terminal delivers a refresh address of 8 bits during the HSYNC signal being low.
  • the MA signal is an output signal indicative of a memory address (upper 6 bits).
  • the DISP signal is an output signal indicative of a display period of the screen.
  • the CUD signal is an output signal for display of a cursor on the CRT screen.
  • the FBREQ signal is an input signal for requesting use of the bus which permits the processing system including the CPU 11 to directly, not through the GDP 10, access the frame buffer 14.
  • the FBREQ signal becomes low, the GDP 10 releases only the drawing cycle.
  • the DISPAS signal is outputted as a timing signal adapted to latch an address signal for display.
  • the GDP 10 delivers the display address.
  • FIG. 5 lists up specified registers and a RAM directly accessible from the CPU 11. With both the RS and CS signals being at the "Low" level, an address register (write only) and a status register (read only) are permitted for accessing. During writing, the address register is selected and during reading, the status register is selected. In FIG. 5, the other registers than the address register and status register are accessed for read/write when the RS signal becomes high and the CS signal becomes low after a register number is designated by the address register.
  • Registers and RAM for control of drawing are accessed by way of FIFOs (first in first out).
  • a write FIFO of 8 words and a read FIFO of 8 words are employed.
  • write to the write FIFO is established and when a read operation is executed, read from the read FIFO is established.
  • the write FIFO handles the command and each time one command processing ends, the next command is transferred to a command register.
  • a pattern RAM is accessed by a WPTN (write pattern RAM) command and an RPTN (read pattern RAM) command.
  • a drawing parameter register is accessed by a WPR (write parameter register) command and an RPR (read parameter register) command.
  • FIG. 6 details the construction of the drawing parameter register.
  • the address register (AR) is a write only register adapted to designate addresses ($00 to $FF) of a control register included in the GDP 10. $ means hexadicimal notation.
  • $ means hexadicimal notation.
  • the contents of the AR is automatically incremented by +1 (during the 8-bit interface) or by +2 (during the 16-bit interface) in response to read or write of the control register. Therefore, a control register having consecutive addresses can be accessed by merely executing the initial write of the head address of the control register to the AR.
  • the status register is a read only register indicative of the internal status of the GDP 10. By executing the reading when both the RS and CS signals are at the "Low” level, the SR can be selected.
  • a FIFO status represents the number of words writable into the write FIFO.
  • Each of the lower 8 bits of the SR being set to "1" has the following meaning. When the individual bits excepting bit 4 are set to "1", there occurs an interruption generating factor. An interrupt enable bit of the command control register then controls generation of an interruption.
  • the CER is cleared by setting an ABT (abort) bit to "1".
  • the ARD Indicates that an area has been detected in accordance with designation for the drawing area test mode.
  • the ARD is cleared by executing a read parameter register (RPR) command or by setting the ABT bit to "1".
  • RPR read parameter register
  • the WFR is cleared when a data of 8 words (16 bytes) is written into the write FIFO.
  • the WFE Indicates that the write FIFO is empty.
  • the WFE is cleared by writing a data into the write FIFO.
  • a FIFO entry is a register for writing a command/parameter into the GDP 10 and for reading a data from the GDP 10.
  • the GDP 10 incorporates a read FIFO of 16 bytes and a write FIFO of 16 bytes.
  • the read FIFO is selected and when a FIFO entry address is set into the address register and writing is executed, the write FIFO is selected.
  • Commands are sequentially executed by writing a command/parameter into the write FIFO and after execution of a read command, the read FIFO sequentially prepares for read data.
  • a command control register is a readable/writable register for controlling the command processing and permission/inhibition of an interruption.
  • Set in the interruption request enable bit within the CCR are seven types of permission/inhibition of interruption request corresponding to seven interruption factors of the status register. By setting "0" into a bit corresponding to a bit position of the status register, an interruption request is inhibited and by setting "1", an interruption request is permitted. Accordingly, by setting interrupt enable bits (IE), interruption request conditions complying with the system ca be set.
  • IE interrupt enable bits
  • the master/slave bit is used as a bit for setting the GDP 10 to be either a master device which is an originator of the sync timing signal of the system or a slave device which depends for operation upon the sync timing signal from another system.
  • the ACP bit is used to set whether drawing is executed or not during the display period.
  • the cursor display skew bit sets the amount of skew of the CUD signal in unit of memory cycle.
  • the CUD signal is delayed within the LSI for a time necessary to access the frame buffer so as to be placed in phase with a serial video signal outputted from the parallel-serial video converter.
  • the RAM mode bit sets the presence or absence of a DRAM refresh address to be outputted to elements of the frame buffer 14 used in the system. By setting the RAM bits to "0", a DRAM refresh address of 8 bits is outputted from the MAD terminals during the "Low” level period of the HSYNC signal.
  • the GAI bits set a mode of increment of a display address output signal to a screen determined as a graphic screen setting in the frame buffer 14. If a data to be read out of one display cycle frame buffer is fixed as one word, the number of pixels which can be displayed per one word is four when a 4 bits/screen configuration is set by the GBM bits. Consequently, in order to make a display on a display unit such as a CRT display of definition equivalent to one bit/pixel or 16 pixels/word, the rate of the input clock to the GDP 10 must be quadrupled. Further, in applications of higher degree of multi-color/multi-gradation, a higher rate of clock is needed.
  • a data of several words is read out of the frame buffer 14 at one display cycle. For example, where a 4 bits/pixel mode is set by the GBM bits, a 64-bit (4-word) data for 16 pixels is read out of the frame buffer 14 at one display cycle and the display address is counted up at the rate of +4 increment. For reading one word (16 bits) at one display cycle, "000" is set into the GAI bits. Where a data of 32 bits, 64 bits or 128 bits is desired to be read at one display cycle in a high-definition or multi-color/multi-gradation system, "001", "010” or “011” is set into the GAI bits.
  • the GDP 10 accesses the frame buffer 14 for read/write in two access modes in accordance with the frame buffer access mode (ACM) bit.
  • ACM frame buffer access mode
  • Raster Scan Mode RSM Bit 1 and Bit 0
  • the raster scanning mode of the GDP 10 is set in accordance with the RSM bits.
  • rasters for odd fields scan so as to interpolate rasters for even fields. Scanning is controlled such that a character or graphic pattern displayed with the even field rasters is identical to that displayed with the odd field rasters.
  • the same raster scanning as that of the interlace sync mode is effected but scanning is controlled such that a character or graphic pattern displayed with the even field rasters is different from that displayed with the odd field rasters.
  • the display control register is a readable/writable register for setting information indicative of display mode and attribute of the screen.
  • the base screen enable bit (BE) sets permission/inhibition of display of the base screen.
  • Attribute Control Information ATR Bit 7 and Bit 0
  • the attribute control information (ATR) bits form a bit code of 8 bits for setting a desired code defined by the user.
  • the ATR information is outputted from the MAD terminal MAD 7 to MAF D 0 immediately before the HSYNC signal changes from "Low" level to "High” level. Since the ATR information is outputted for each raster, it can be utilized in an application of attribute control in unit of raster by dynamically rewriting the contents of the ATR bits. Namely, ATR is rewrited during display period.
  • the raster count register is for storing a number of a raster (raster line) which the display unit currently scans.
  • the CPU can read the RCR at a desired time to know the present scanning position.
  • HDS horizontal display start position
  • HDW horizontal display width
  • the X-axis direction (horizontal direction) is defined by the number of memory cycles counted from the rise of the HSYNC signal and the Y-axis direction (vertical direction) is defined by the number of rasters counted from the rise of the HSYNC signal.
  • the memory width is set in unit of memory address.
  • a display start dot address (SDA) can also be set into the SAR and delivered to the MAD terminals MAD 8 to MAD 11, as information for controlling an external circuit adapted to effect horizontal smooth scrolling, in synchronism with the rise of the HSYNC signal. Based on this information, the external circuit controls load timing or load data for the parallel-serial converter t thereby perform the horizontal smooth scrolling
  • CON ON timing
  • COFF OFF timing
  • the CCMP Defines an evaluation color for drawing operation.
  • the CCMP is used for defining a specified background color or a drawing inhibition color.
  • SRCH search command
  • TDOT test dot command
  • Pattern RAM used for drawing and a start point of pattern RAM scanning.
  • a pattern area a desired area of 16 dots ⁇ 16 dots at the most can be set.
  • a reference area of the pattern RAM used can be defined by pattern start position bits (PSX, PSY) and pattern end position bits (PEX, PEY) in the X and Y directions.
  • pattern zoom coefficient bits PZX, PZY
  • zoom coefficients for pattern reference are defined.
  • Pattern point bits (PPX, PPY) store the current reference point position of the pattern RAM and can be used to designate a desired reference start point before issuance of a drawing command.
  • Pattern zoom count bits (PZCX, PZCY) indicate a count value of zoom rate for pattern reference.
  • the number of font bits in the X direction is set by FSX bits and the number of font bits in the Y direction is set by FSY bits.
  • the DP is a pointer which manages a linear address of a current drawing point.
  • CP current pointer
  • the DP manages a drawing number (DN), a drawing pointer address (DRAH, DPAL) and a drawing pointer bit address (DPB).
  • DN drawing number
  • DRAH drawing pointer address
  • DPAL drawing pointer bit address
  • a mode of drawing There are available a drawing area detecting mode for drawing management of the frame buffer area, a color data developing mode, a color data operation mode, and a pel mode for defining the size of one pixel for line drawing.
  • FIG. 7 illustrates an example of the operation of a PUT command.
  • the PUT command is to transfer a data from the main memory 12 to a rectangular region representing pixels in the frame buffer 14.
  • the rectangular region of the frame buffer 14 is defined by the coordinates of two points located at opposite corners of the rectangle.
  • One of the points has coordinates designated by the current pointer CP and the other point has relative coordinates designated by parameters LX and LY.
  • LX the bits are aligned in a row in the X direction. Therefore, if the number of bits indicated by the parameter LX is not a multiple of the number of bits representative of one word in the main memory 12, then an invalid data occurs as shown in FIG. 7.
  • FIG. 8 shows an example of the operation of a GET command.
  • the GET command is to transfer data from a rectangular region representing pixels in the frame buffer memory 14 to the main memory 12.
  • the rectangular region of the frame buffer 14 is similarly defined as above as having two diagonal points one of which has coordinates designated by the current pointer CP and the other of which has relative coordinates designated by parameters LX and LY.
  • LX coordinates designated by the current pointer CP
  • LY relative coordinates designated by parameters
  • FIG. 9 illustrates an example of the operation of an ELARC command.
  • the ELARC command is for drawing an ellipse centered on coordinates CPX and CPY designated by the current pointer CP.
  • a drawing region is defined by a line segment connecting the coordinates designated by the CP with relative coordinates designated by parameters Xs and Ys and a line segment connecting the coordinates designated by the CP with relative coordinates designated by parameters Xe and Ye.
  • the maximum drawing region is defined by the major axis of the ellipse and the minor axis.
  • As operation start points one of four points on the major and minor axes of the elipse are designated by parameters SP.
  • the CPU 11 can read the drawing start point and the drawing end point by way of the FIFO.
  • FIG. 10 exemplifies the operation of an FEFAN command which is for painting a fan centered on coordinates CPX and CPY designated by the CP by using a graphic image stored in the pattern RAM.
  • This command contains parameters having the same meaning as that of the ELARC command.
  • FIG. 11 depicts an example of the maximum drawing region defined by the fan obtained with this command FEFAN.
  • FIG. 12 exemplifies the operation of an FTR1 command.
  • the FTR1 command paints a triangle having as apices three points defined by coordinates designated by the CP, absolute coordinates designated by parameters X1 and Y1 and absolute coordinates designated by parameters X2 and Y2.
  • a desired polygon can be filled with desigh patterns.
  • FIG. 13 exemplifies the operation of a ZOOM command.
  • the ZOOM command is for transferring, with enlargement or reduction, a rectangular region having diagonal two points, one of which has absolute coordinates designated by parameters XS and XY and the other of which has coordinates relative to the absolute coordinates that are designated by parameters LSX and LSY, to a rectangular region having diagonal two points one of which has coordinates designated by the CP and the other of which has relative coordinates designated by parameters LDX and LDY.
  • the magnification in the X direction is represented by the ratio between LSX and LDX
  • the magnification in the Y direction is represented by the ratio between LSY and LDY.
  • the X-direction magnification and the Y-direction magnification can be set independently of each other.
  • FIG. 14 illustrates an example of the operation of an ROT command.
  • the ROT command is to transfer, with rotation, a rectangular region having diagonal two points, one of which has absolute coordinates designated by parameters XS and YS and the other of which has coordinates relative to the absolute coordinates designated by parameters LSX and LSY, to a region defined by coordinates designated by the CP and parameters LDX 1, LDX 2, LDY 1 and LDY 2.
  • ⁇ Assuming that the rotation angle is ⁇ , these parameters as indicated by the following equations are inputted:
  • FIG. 15 illustrates an interpolation processing for the ROT command.
  • no interporation is performed.
  • X and Y coordinates of a pointer for determining a coordinate position of transfer destination are both renewed, a pixel data at a coordinate X immediately preceding the renewed coordinate X is copied at the renewed coordinate X.
  • FIG. 16 illustrates an example of the operation of a TEXT command.
  • the TEXT command is used in a system utilizing part of the frame buffer 14 as the character font area, for developing a character font data corresponding to an inputted command code at a position in the display area of frame buffer 14 which is designated by the current pointer.
  • the internal registers of the GDP 10 that is, the registers FSAH and FSAL for setting a start address of a font area and the register FAMW for setting a memory width of the font area, registers FSX and FSY for setting widths of a character actually developed, a register FBN for setting the total number of bits for one character, and a register CHS for setting a spacing between adjacent characters in the X direction are all set in advance.
  • the CPU 11 transfers the TEXT command and a parameter n representative of the number of characters to be developed, followed by sequential transfer of character codes CN representative of n characters.
  • the GDP 10 generates the addresses of the individual character fonts corresponding to the character codes CN to develop them and transfers and writes pixel information of each corresponding character font pattern to a predetermined storing position in the display area of frame buffer 14 corresponding to a predetermined display position on the display unit 16.
  • FIG. 17 shows an example of color development in the mode of the TEXT command.
  • This example provides a method for converting a font data which is a binary data into a color data which is of multi-level information.
  • a color register 0 and a color register 1 are internal registers of the GDP 10 and they are respectively set with a color data corresponding to "0" of the font data and a color data corresponding to "1" of the font data.
  • the GDP sequentially retrieves the read font data and writes a color data corresponding thereto into the frame buffer 14.
  • FIG. 18 exemplifies the operation of a TEXTPS command which sets, in addition to the function of the TEXT command, a development width of a character in the X direction.
  • the development width is controlled by storing a code indicating a development width in the X direction into the upper byte of a parameter CC and a character code into the lower byte of the parameter CC.
  • FIG. 19 schematically exemplifies a system for character font development by using the TEXT command or the TEXTPS command.
  • FIGS. 20 and 21 illustrate an example of the operation of an APMV command.
  • the APMV command is used to simultaneously move coordinates PPX and PPY designated by a pattern pointer to coordinates PX and PY designated by a reference point stored in the pattern RAM.
  • FIGS. 22 and 23 illustrates the operation of an RPMV command.
  • the RPMV command is used to simultaneously move coordinates PPX and PPY designated by the pattern pointer.
  • FIG. 24 depicts scanning directions determined by an SRCH command.
  • the SRCH command is subject to a parameter EP having the meaning as illustrated in FIG. 25.
  • the SRCH command detects an edge color designated by the parameter I and sets the detected point into the CP and pattern pointer.
  • the edge color is identical to an edge color indicated by a data of the edge color register EDG and when the parameter I is "1", the edge color becomes a color different from that indicated by the data of the register EDG.
  • a parameter EP indicates limits imposed on scanning and is set with the maximum coordinate X of a scanning region during X-direction scanning and with the maximum coordinate Y of the scanning region during Y-driection scanning.
  • FIG. 26 illustrates an example of the operation of a TDOT command.
  • the TDOT command reads a color data indicated by the CP and causes a comparator in GDP 10 to compare that data with an edge value designated by the parameter I, thus setting a comparison result into the status register.
  • the edge color corresponds to the data of the EDG register and when "1", the edge color corresponds to a different data from that of the EDG register.
  • FIG. 27 illustrates at section (A) an example of the operation of a COPY command.
  • the COPY command is for copying, within the frame buffer 14, a data representative of a rectangular region being parallel with the coordinate axes and having diagonal two points, one of which has absolute coordinates relative to the origin designated by parameters XS and YS and the other of which has coordinates relative to the absolute coordinates designated by parameters LX and LY, to a rectangular region being parallel with the coordinate axes and having a start point designated by the CP.
  • FIG. 27 illustrates at section (B) the scanning directions of the COPY command within the transfer originating region and the transfer destination region. The scanning directions are determined by signs of the parameters LX and LY and they are coincident with each other within the transfer originating and destination regions.
  • FIG. 28 shows a transfer model in unit of word executable by the COPY command.
  • the GDP 10 in accordance with the foregoing embodiment can handle the highly functional command system and greatly relieve the amount of processings charged on the CPU 11. This permits the graphic processing system to have facility of high performance. In addition, by providing the GDP 10 in the form of the LSI, cost reduction of the graphic processing system can also be ensured.
  • a graphic processing system comprises a central processing unit (CPU) 11, a main memory 12, a graphic drawing processor (GDP) 10, a frame buffer 14, a memory interface controller (GMIC) 20, a video attribute controller 30, and a display unit 16 such as a CRT.
  • CPU central processing unit
  • main memory main memory
  • GDP graphic drawing processor
  • frame buffer 14
  • GMIC memory interface controller
  • video attribute controller 30
  • display unit 16 such as a CRT.
  • the CPU 11 transfers to the GDP 10 a graphic processing command and parameter information and starts the GDP 10.
  • the GDP 10 processes to prepare a graphic data on the frame buffer in accordance with a predetermined processing procedure.
  • the GMIC 20 responds to a frame buffer access of the GDP 10 to generate a memory control signal.
  • the display data is read out of the frame buffer and converted by the GVAC 30 into a video signal which in turn is sent to the CRT 16.
  • the GMIC 20 and the GVAC 30 mainly provide memory controlling and video signal controlling, respectively, and they are provided in the form of LSI's.
  • the GDP 10 provided as the LSI though its detailed circuit has not been illustrated in FIG. 1, is associated with a great number of peripheral logical gates used for memory controlling and video signal controlling.
  • the GMIC 20 can be connected directly to the GDP 10 and frame buffer 14, and the GVAC 30 can be connected directly to the GDP 10 to the frame buffer 14 and CRT 16. Functions of the two will be detailed below.
  • the GMIC 20 comprises a memory address controller 201, an attribute controller 202, a timing controller 203, a clock generator 205, and a zoom controller 204.
  • the memory address controller 201 delivers an address of frame buffer 14 outputted from the GDP 10 as a composite signal of a row address and a column address of a dynamic RAM.
  • the attribute controller 202 temporarily stores attribute information outputted from the GDP 10 and sends control information to the timing controller 203.
  • the timing controller 203 generates various signals for controlling the dynamic RAM and prepares a signal for controlling generation of a video signal corresponding to horizontal smooth scrolling.
  • the clock generator 205 Based on a preset frequency division rate, the clock generator 205 generates a clock signal outputted to the GDP 10.
  • the zoom controller 204 generates a video generation control signal for horizontal zoom display on the basis of information from the attribute controller.
  • FIG. 31 shows input and output signals of the GMIC 20 shown in FIG. 30.
  • Functions of terminals, bus and individual signals are as follows.
  • the terminal Vss is applied with ground potential and the terminal Vcc with +5V.
  • the MRD input signal is for controlling the direction of data transfer between the GDP 10 and frame buffer 14 during the drawing cycle and used to generate signals "WE 0 to WE 3" which control write of data to the frame buffer 14.
  • the MRD signal is high, the GDP 10 reads the frame buffer 14 and when low, the GDP 10 writes the frame buffer 14.
  • An output signal to which the internal operation of the GDP 10 is referenced Generated by dividing a clock of a frequency which is n times the memory access timing frequency (memory cycle) of the frame buffer 14 at a frequency dividing rate determined by an externally inputted DOTCK signal which is set in accordance with CDM0 and CDM1 signals to be described later.
  • the IM signal sets increment modes of the display address.
  • the IM signal is set in accordance with a graphic address increment mode of the GDP 10.
  • the IM signal is also used as a control signal for multiplexing row and column addresses of the dynamic RAM.
  • the CDM input signal is for dividing the externally inputted DOTCK signal to prepare the CLK signal outputted to the GDP 10 and sets the frequency dividing ratio of the CLK signal.
  • n 2 (single access mode)
  • n 4 (dual access mode)
  • the DOTCK signal is a high rate clock signal having one cycle which corresponds to one pixel display period.
  • a clock signal for controlling the parallelserial converter used for generation of video signals is generated by controlling the frequency of the externally inputted DOTCK signal in accordance with a horizontal zoom rate which is attribute information outputted from the GDP 10.
  • the SLD 1 signal is a load timing signal of normal display timing and the SDL 2 signal is a load timing signal which provides output timings varying with the amounts of horizontal smooth scrolling which is attribute information outputted from the GDP 10.
  • the frame buffer 14 is indicated to be a dynamic RAM and when low, the frame buffer 14 is indicated to be a shifter built-in type dual port memory (VRAM).
  • VRAM shifter built-in type dual port memory
  • the DT/OE signal is an out-enable signal for the RAM when the GDP 10 accesses the frame buffer 14 and controls read of data from the RAM.
  • the DT/OE signal causes a signal for controlling data transfer to a shifter within the VRAM to be delivered out.
  • the WE signal is for controlling write of a drawing data from the GDP 10 to the frame buffer 14. With the WE signal being at the "Low” level, write of the drawing data is indicated.
  • the A signal is for indicating a specified one word when data transfer is executed between the GDP 10 and the frame buffer 14. By using the A signal, data transfer of a desired address can be ensured.
  • RAM address RAM (RAMA 7 to RAMA 0: output)
  • An output signal indicative of a timing for latching a row address outputted to the frame buffer is an output signal indicative of a timing for latching a row address outputted to the frame buffer.
  • An output signal indicative of a timing for latching a column address outputted to the screen is an output signal indicative of a timing for latching a column address outputted to the screen.
  • An input signal indicative of a display period of the screen In the VRAM mode, the DISP signal is used for generating a DT/OE signal for data transfer control.
  • the SBL signal is used to cause the GMIC to prepare the load timing signals SLD (SLD 1 and SLD 2) for generation of the video signal.
  • These four bits set a zoom display coefficient for horizontal zoom display.
  • the GVAC 30 comprises a data bus buffer 301, a timing controller 302, a display data latch 303, a parallel-serial converter 304, and a video signal output port 305.
  • the data bus buffer 301 is externally instructed to control data transfer between the GDP 10 and the frame buffer 14.
  • Various timing signals are supplied to the GVAC 30 through the timing controller 302.
  • the display data latch 303 temporarily stores display data read out of the frame buffer 14 and then supplies the display data to the parallel-serial converter 304.
  • the parallel-serial converter 304 responds to an externally inputted timing signal to convert the parallel display data into a serial data.
  • the video signal output port 305 delivers to the CRT 16 the serial data as a video signal.
  • FIG. 33 shows input and output signals of the GVAC 30. Functions of terminals, bus and individual signals are as follows.
  • the terminal Vss is grounded and the terminal Vcc is supplied with +5V.
  • the MRD input signal is for controlling the direction of data transfer between the GDP 10 and frame buffer 14 during the drawing cycle and used as a data transfer control signal within the data bus buffer.
  • An input signal indicative of a display period of the screen is used for controlling delivery of the video signal.
  • the direction of the data transfer by this signal is controlled by the MRD signal.
  • An SLD input signal is indicative of a timing for setting a data into the parallel-serial converter 304 and inputted externally.
  • Video VIDEO bits VIDEO 3 to VIDEO 0: output
  • a signal for delivering to the CRT 16 a display video signal converted from the parallel-serial converter 304.
  • FIG. 34 shows an example of connection circuit of the graphic processing system utilizing the GMIC 20 and GVAC 30.
  • GVAC 30 and GMIC 20 with programmable faculties, a variety of graphic processing systems can be constructed easily with a small number of parts.
  • the present invention can advantageously realize a graphic processing system with high speed character processing performance.

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US06/905,173 1985-09-13 1986-09-09 Graphic processing system for displaying characters and pictures at high speed Expired - Lifetime US4947342A (en)

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JPH0762794B2 (ja) 1995-07-05
KR870003459A (ko) 1987-04-17
DE3689917D1 (de) 1994-07-21
KR960000884B1 (ko) 1996-01-13
EP0215428A2 (fr) 1987-03-25
DE3689917T2 (de) 1994-09-22
US6538653B1 (en) 2003-03-25
EP0215428A3 (en) 1990-03-28
JPS6262390A (ja) 1987-03-19
US5751930A (en) 1998-05-12
EP0215428B1 (fr) 1994-06-15

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