US5105261A - Semiconductor device package having particular lead structure for mounting multiple circuit boards - Google Patents

Semiconductor device package having particular lead structure for mounting multiple circuit boards Download PDF

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Publication number
US5105261A
US5105261A US07/758,719 US75871991A US5105261A US 5105261 A US5105261 A US 5105261A US 75871991 A US75871991 A US 75871991A US 5105261 A US5105261 A US 5105261A
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US
United States
Prior art keywords
semiconductor device
package
leads
plane
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US07/758,719
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English (en)
Inventor
Tetsuya Ueda
Toru Tachikawa
Masataka Takehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: TAKEHARA, MASATAKA, TACHIKAWA, TORU, UEDA, TETSUYA
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Publication of US5105261A publication Critical patent/US5105261A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H10W70/427—Bent parts
    • H10W70/429—Bent parts being the outer leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10946—Leads attached onto leadless component after manufacturing the component
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present invention relates to a semiconductor device and a method of mounting the same and, more particularly, to the configuration of a lead of a semiconductor device and a method of mounting the semiconductor device having the lead of such a configuration.
  • FIG. 1 is a partially cutaway perspective view showing a conventional DIL (Dual In Line Package) type semiconductor device which has leads arranged in parallel and extending downward from opposite sides of a package.
  • this DIL type semiconductor device 1a comprises a semiconductor element 2 fixed on a die pad 3 for supporting the semiconductor element 2 by means of solder material 4.
  • the semiconductor element 2 has electrodes (not shown) which are connected with leads 5 through thin metal wires 6. Portions of the leads 5 to be connected with the wires 6 are provided with plating such as Ag plating in order to ensure the connection.
  • the semiconductor element 2 and the wires 6 are sealed with mold resin 7 which forms a plastic package for protection against external forces. After the completion of the package 7, the leads 5 are cut away from a lead frame (not shown) and ends 5a of the leads 5 projecting from the package 7 are bent perpendicularly to the package 7.
  • FIG. 2B is a front view showing the DIL type semiconductor device 1a mounted on a printed circuit board 8.
  • FIG. 2C is a side view of FIG. 2B and
  • FIG. 2A is a fragmentary enlarged view of FIG. 2B.
  • the leads 5 are inserted into through holes 11 of the board 8 from the upper side of the board 8, and then solder 10 is supplied in the through holes 11 from the lower side of the board 8 to connect the leads 5 with leads 9.
  • the semiconductor device 1a is mounted on the board 8.
  • the leads 9 are connected with other devices and the like (not shown) mounted on the board 8 through a wiring pattern (not shown) formed on the board 8.
  • FIG. 3 is a partially cutaway perspective view showing a conventional ZIL (Zigzag In Line Package) type semiconductor device which has leads extending from one side of a package which are bent alternately on two planes in a zigzag manner.
  • This ZIL type semiconductor device 1b is mounted on a printed circuit board 8 as shown in FIG. 4, wherein FIG. 4B is a front view, FIG. 4C is a side view of FIG. 4B and FIG. 4A is a fragmentary enlarged view of FIG. 4B.
  • Reference numerals 2 to 11 in FIG. 3 and FIG. 4 denote the same components as in FIG. 1 and FIG. 2.
  • the DIL type semiconductor device shown in FIG. 1 and the ZIL type semiconductor device shown in FIG. 3 are called through hole devices because these devices are mounted on the board 8 by inserting the leads 5 into the through holes 11.
  • FIG. 5 is a partially cutaway perspective view showing a conventional SOP (Small Outline Package) type semiconductor device which has steplike leads arranged in parallel which are extending from opposite sides of a package.
  • This SOP type semiconductor device 1c is mounted on a printed circuit board 8 as shown in FIG. 6, wherein FIG. 6B is a front view, FIG. 6C is a side view of FIG. 6B and FIG. 6A is a fragmentary enlarged view of FIG. 6C.
  • Reference numerals 2 to 10 in FIG. 5 and FIG. 6 denote the same components as in FIG. 1 to FIG. 4.
  • the SOP type semiconductor device shown in FIG. 5 is called a surface mounting type device (SMD) because this device is mounted on the board 8 without through holes.
  • SMD surface mounting type device
  • the conventional semiconductor devices structured as hereinbefore described can not be mounted across a plurality of printed circuit boards not lying on the same plane.
  • a semiconductor device in accordance with the present invention comprises a semiconductor element, a package for sealing the semiconductor element and leads electrically connected with the semiconductor element, the leads projecting from at least two (first and second) sides of the package and being bent in a zigzag manner so that the ends of the leads lie on at least two (first and second) planes.
  • This semiconductor device may be mounted across a plurality of printed circuit boards in accordance with a method of mounting a semiconductor device according to the present invention, comprising the steps of preparing first and second printed circuit boards, fixing a first group of the leads projecting from the first side of the package to the first printed circuit board, and fixing a second group of the leads projecting from the second side of the package to the second printed circuit board.
  • This semiconductor device may also be mounted across a plurality of printed circuit boards in accordance with a method of mounting a semiconductor device according to the present invention, comprising the steps of preparing first and second printed circuit boards, fixing a first group of the leads lying on the first plane to the first printed circuit board, and fixing a second group of the leads lying on the second plane to the second printed circuit board.
  • FIG. 1 is a partially cutaway perspective view showing a conventional DIL type semiconductor device
  • FIG. 2A to FIG. 2C are views showing the DIL type semiconductor device mounted on a printed circuit board
  • FIG. 3 is a partially cutaway perspective view showing a conventional ZIL type semiconductor device
  • FIG. 4A to FIG. 4C are views showing the ZIL type semiconductor device mounted on a printed circuit board
  • FIG. 5 is a partially cutaway perspective view showing a conventional SOP type semiconductor device
  • FIG. 6A to FIG. 6C are views showing the SOP type semiconductor device mounted on a printed circuit board
  • FIG. 7 is a partially cutaway perspective view showing a first embodiment of a semiconductor device in accordance with the present invention.
  • FIG. 8 is a partially cutaway perspective view showing the semiconductor device of the first embodiment before the completion thereof;
  • FIG. 9A to FIG. 9C are plane, side and front views, respectively, showing the semiconductor device of the first embodiment
  • FIG. 10A to FIG. 10C and FIG. 11A to FIG. 11C are views showing the semiconductor device of the first embodiment mounted across two printed circuit boards;
  • FIG. 12 is a partially cutaway perspective view showing a second embodiment of the semiconductor device in accordance with the present invention.
  • FIG. 13 is perspective view showing a third embodiment of the semiconductor device in accordance with the present invention.
  • FIG. 14A to FIG. 14C are plane, side and front views, respectively, showing a fourth embodiment of the semiconductor device in accordance with the present invention.
  • FIG. 7 is a partially cutaway perspective view showing an embodiment of a semiconductor device in accordance with the present invention.
  • this semiconductor device 1 comprises a semiconductor element 2 fixed on a die pad 3 for supporting the semiconductor element 2 by means of solder material 4.
  • the semiconductor element 2 has electrodes (not shown) which are connected with leads 5 through thin metal wires 6. Portions of the leads 5 to be connected with the wires 6 are provided with a plating such as an Ag plating in order to ensure the connection.
  • the semiconductor element 2 and the wires 6 are sealed with mold resin 7 which forms a plastic package for protection against external forces. After the completion of the package 7, the leads 5 are cut away from a lead frame (not shown). At this stage, the semiconductor device 1 has a structure shown in FIG. 8.
  • FIG. 9A is a plane view of the completed semiconductor device 1 and FIG. 9B and FIG. 9C are side and front views of FIG. 9A, respectively. Ends of leads 5b of the leads 5 lie on a first plane in the top surface side of the semiconductor device 1 and ends of leads 5c of the leads 5 lie on a second plane in the rear surface side of the semiconductor device 1.
  • the semiconductor device 1 structured as hereinbefore described may be mounted across two printed circuit boards 8a and 8b as shown in FIG. 10, wherein FIG. 10A is a front view, FIG. 10B is a side view and FIG. 10C is a plane view. In FIG. 10C, the upper printed circuit board 8a is deleted for the purpose of illustrating the semiconductor device 1.
  • the semiconductor device 1 is placed between and perpendicularly to the two parallel printed circuit boards 8a and 8b.
  • a half of the leads 5 projecting from one side of the package which are arranged in an alternate zigzag manner are inserted in through holes 11 of the upper board 8a to be fixed to the board 8a by means of solder 10 supplied in the through holes 11.
  • a remaining half of the leads 5 projecting from the other side of the package which are arranged in an alternate zigzag manner are inserted in through holes 11 of the lower board 8b to be fixed to the board 8b by means of solder 10 supplied in the through holes 11.
  • the semiconductor device 1 may also be mounted across two printed circuit boards 8a and 8b as shown in FIG. 11, wherein FIG. 11A is a plane view, FIG. 11B is a side view and FIG. 11C is a front view.
  • FIG. 11A the upper printed circuit board 8a is deleted for the purpose of illustrating the semiconductor device 1.
  • the semiconductor device 1 is placed between and parallel to the two parallel printed circuit boards 8a and 8b.
  • a half of the leads 5 lying on one plane in the top surface side of the device 1 are fixed on the upper board 8a by means of solder 10.
  • a remaining half of the leads 5 laying on the other plane in the rear surface side of the device 1 are fixed on the lower board 8b by means of solder 10.
  • the semiconductor device 1 can be mounted across the two parallel printed circuit boards 8a and 8b which are perpendicular to or parallel to the leads 5 of the semiconductor device 1.
  • FIG. 12 is a partially cutaway perspective view showing another embodiment of the semiconductor device in accordance with the present invention, wherein a ceramic package 12 is employed.
  • the ceramic package 12 is composed of two parts of an upper part 12a and a lower part 12b. Leads 5 extend outside through between the upper and lower parts 12a and 12b of the ceramic package 12. Leads 5 and the upper and lower parts 12a and 12b of the ceramic package 12 are attached by means of sealant 13.
  • a metal cover 14 is provided on the upper part 12a of the ceramic package 12 to close a cavity provided in the ceramic package 12.
  • Other structures are the same as those of the semiconductor device shown in FIG. 7.
  • FIG. 13 is a perspective view showing a third embodiment of the semiconductor device in accordance with the present invention, wherein leads 5 are projected from four sides of a package 7 as compared with that in which the leads 5 are provided only at two sides (opposite sides) of the package 7, as shown in the first and second embodiments.
  • Other structures are the same as those of the semiconductor device shown in FIG. 7.
  • FIG. 14A to FIG. 14C are plane, side and front views, respectively, showing a fourth embodiment of the semiconductor device in accordance with the present invention, wherein leads 5 are bent in a zigzag manner so as to lie on four planes as compared with that in which the leads 5 lie on two planes, as shown in the first to third embodiments.
  • Other structures are the same as those of the semiconductor device shown FIG. 7.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
US07/758,719 1989-03-30 1991-09-09 Semiconductor device package having particular lead structure for mounting multiple circuit boards Expired - Fee Related US5105261A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-80485 1989-03-30
JP1080485A JPH02260450A (ja) 1989-03-30 1989-03-30 半導体装置およびその実装方法

Related Parent Applications (1)

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US07446140 Continuation 1989-12-05

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US07/758,719 Expired - Fee Related US5105261A (en) 1989-03-30 1991-09-09 Semiconductor device package having particular lead structure for mounting multiple circuit boards

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557145A (en) * 1994-03-11 1996-09-17 Fujitsu Limited Mounting construction and method of a semiconductor device by which deformation of leads is prevented
US5625221A (en) * 1994-03-03 1997-04-29 Samsung Electronics Co., Ltd. Semiconductor assembly for a three-dimensional integrated circuit package
US5754405A (en) * 1995-11-20 1998-05-19 Mitsubishi Semiconductor America, Inc. Stacked dual in-line package assembly
US6100580A (en) * 1988-09-20 2000-08-08 Hitachi, Ltd. Semiconductor device having all outer leads extending from one side of a resin member
US6323545B1 (en) * 1997-10-07 2001-11-27 Mitsubishi Denkikabushiki Kaisha Semiconductor device
US20040155323A1 (en) * 1988-09-20 2004-08-12 Gen Murakami Semiconductor device
CN104617071A (zh) * 2015-01-19 2015-05-13 株洲南车时代电气股份有限公司 功率端子组及功率电子模块
EP3264457A1 (en) * 2016-06-30 2018-01-03 NXP USA, Inc. Packaged semiconductor device having a lead frame and inner and outer leads and method for forming
US11682609B2 (en) * 2019-06-29 2023-06-20 Texas Instruments Incorporated Three-dimensional functional integration
WO2023174984A1 (de) * 2022-03-17 2023-09-21 Iie Gmbh & Co. Kg Elektronische schaltung und verfahren zu deren herstellung, sowie verbesserter aktiver leistungshalbleiter zum einbau in die elektronische schaltung und verfahren zu dessen herstellung

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6371110B2 (ja) * 2014-05-15 2018-08-08 ローム株式会社 両面接続用実装パッケージ

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55107251A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Electronic part and its packaging construction
JPS5915500A (ja) * 1982-07-17 1984-01-26 ライオン株式会社 固型皮膚洗浄剤組成物
JPS5963751A (ja) * 1982-10-04 1984-04-11 Matsushita Electronics Corp 半導体装置
JPS60103652A (ja) * 1983-11-11 1985-06-07 Hitachi Ltd 半導体装置およびこれに用いられるリ−ドフレ−ム
JPS6352455A (ja) * 1986-08-22 1988-03-05 Hitachi Ltd 封止型半導体装置用リ−ドフレ−ム
US5025307A (en) * 1989-03-30 1991-06-18 Mitsubishi Denki Kabushiki Kaisha Modular semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55107251A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Electronic part and its packaging construction
JPS5915500A (ja) * 1982-07-17 1984-01-26 ライオン株式会社 固型皮膚洗浄剤組成物
JPS5963751A (ja) * 1982-10-04 1984-04-11 Matsushita Electronics Corp 半導体装置
JPS60103652A (ja) * 1983-11-11 1985-06-07 Hitachi Ltd 半導体装置およびこれに用いられるリ−ドフレ−ム
JPS6352455A (ja) * 1986-08-22 1988-03-05 Hitachi Ltd 封止型半導体装置用リ−ドフレ−ム
US5025307A (en) * 1989-03-30 1991-06-18 Mitsubishi Denki Kabushiki Kaisha Modular semiconductor device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100580A (en) * 1988-09-20 2000-08-08 Hitachi, Ltd. Semiconductor device having all outer leads extending from one side of a resin member
US20040155323A1 (en) * 1988-09-20 2004-08-12 Gen Murakami Semiconductor device
US6919622B2 (en) * 1988-09-20 2005-07-19 Renesas Technology Corp. Semiconductor device
US5625221A (en) * 1994-03-03 1997-04-29 Samsung Electronics Co., Ltd. Semiconductor assembly for a three-dimensional integrated circuit package
US5557145A (en) * 1994-03-11 1996-09-17 Fujitsu Limited Mounting construction and method of a semiconductor device by which deformation of leads is prevented
US5693571A (en) * 1994-03-11 1997-12-02 Fujitsu Limited Method for mounting a semiconductor device by which deformation of leads is prevented
US5754405A (en) * 1995-11-20 1998-05-19 Mitsubishi Semiconductor America, Inc. Stacked dual in-line package assembly
US6323545B1 (en) * 1997-10-07 2001-11-27 Mitsubishi Denkikabushiki Kaisha Semiconductor device
CN104617071A (zh) * 2015-01-19 2015-05-13 株洲南车时代电气股份有限公司 功率端子组及功率电子模块
EP3264457A1 (en) * 2016-06-30 2018-01-03 NXP USA, Inc. Packaged semiconductor device having a lead frame and inner and outer leads and method for forming
CN107564821A (zh) * 2016-06-30 2018-01-09 恩智浦美国有限公司 具有引线框和内部引线与外部引线的封装半导体装置和形成方法
US9978669B2 (en) 2016-06-30 2018-05-22 Nxp Usa, Inc. Packaged semiconductor device having a lead frame and inner and outer leads and method for forming
CN107564821B (zh) * 2016-06-30 2024-02-27 恩智浦美国有限公司 具有引线框和内部引线与外部引线的封装半导体装置和形成方法
US11682609B2 (en) * 2019-06-29 2023-06-20 Texas Instruments Incorporated Three-dimensional functional integration
US12074098B2 (en) 2019-06-29 2024-08-27 Texas Instruments Incorporated Three-dimensional functional integration
WO2023174984A1 (de) * 2022-03-17 2023-09-21 Iie Gmbh & Co. Kg Elektronische schaltung und verfahren zu deren herstellung, sowie verbesserter aktiver leistungshalbleiter zum einbau in die elektronische schaltung und verfahren zu dessen herstellung

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