US5914505A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
US5914505A
US5914505A US08/706,394 US70639496A US5914505A US 5914505 A US5914505 A US 5914505A US 70639496 A US70639496 A US 70639496A US 5914505 A US5914505 A US 5914505A
Authority
US
United States
Prior art keywords
circuit
input
circuits
output
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/706,394
Other languages
English (en)
Inventor
Toshiki Hisada
Hiroyuki Koinuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HISADA, TOSHIKI, KOINUMA, HIROYUKI
Application granted granted Critical
Publication of US5914505A publication Critical patent/US5914505A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs

Definitions

  • the present invention relates to a semiconductor integrated circuit. More particularly, the invention relates to an output noise processing circuit in the semiconductor integrated circuit utilized in, for instance, a dynamic type semiconductor memory (DRAM).
  • DRAM dynamic type semiconductor memory
  • output data Dout is output corresponding to the active period of a /CAS (/Column Address Strobe) signal and during other periods an output is placed in a high impedance state (HiZ).
  • Output data Dout in the fast page mode changes between a high level "H” and a high impedance or between a low level “L” and a high impedance.
  • EDO mode Extended Data Output mode
  • FIG. 10 output data Dout is switched in synchronization with the leading edge of a /CAS signal.
  • This mode is advantageous, since a cycle time can be made short by an amount equivalent to widening of an output window width.
  • the present invention has been made to solve the above-noted problem. It is an object of the invention to provide a semiconductor integrated circuit capable of preventing an internal circuit from malfunctioning because of output noises following a change in output data.
  • a semiconductor integrated circuit is provided with the following elements: an input circuit for receiving an input signal from the outside; an internal circuit connected to the input circuit; an output circuit connected to the final stage of the internal circuit for supplying an output signal to the outside; a power supply line connected to each of the circuits; a power supply terminal connected to the power supply line; a first ground conductor connected to the input circuit; a second ground conductor separated from the first ground conductor and connected to the internal circuit; a third ground conductor separated from the first ground conductor and connected to the output circuit; a first ground terminal connected to the first ground conductor; and a second ground terminal connected to the second ground conductor.
  • a semiconductor integrated circuit is provided with the following elements: an input circuit for receiving an input signal from the outside; a succeeding-stage circuit connected to the input circuit; an internal circuit connected to the succeeding-stage circuit; an output circuit connected to the final stage of the internal circuit for supplying an output signal to the outside; a power supply line connected to each of the circuits; a power supply terminal connected to the power supply line; a first ground conductor connected to the input and succeeding-stage circuits; a second ground conductor separated from the first ground conductor and connected to the internal circuit; a first ground terminal connected to the first ground conductor; and a second ground terminal connected to the second ground conductor.
  • a semiconductor integrated circuit is provided with the following elements: a plurality of input circuits for respectively receiving different input signals from the outside; a plurality of succeeding-stage circuits respectively connected to the plurality of input circuits in a corresponding manner; an internal circuit connected to the succeeding-stage circuits; a plurality of output circuits connected to the final stage of the internal circuit for supplying output signals to the outside; a power supply line connected to each of the circuits; a power supply terminal connected to the power supply line; a first ground conductor connected to the plurality of input circuits and some of the plurality of succeeding-stage circuits; a second ground conductor separated from the first ground conductor and connected to the internal circuit and the rest of the plurality of succeeding-stage circuits; a first ground terminal connected to the first ground conductor; and a second ground terminal connected to the second ground conductor.
  • a semiconductor integrated circuit is provided with the following elements: an input circuit for receiving an input signal from the outside; an internal circuit connected to the input circuit; an output circuit connected to the internal circuit for outputting an output signal to the outside; a power supply line connected to each of the circuits; a power supply terminal connected to the power supply line; a first ground conductor connected to the input circuit; a second ground conductor separated from the first ground conductor and connected to the internal and output circuits; a first ground terminal connected to the first ground conductor; and a second ground terminal connected to the second ground conductor.
  • a semiconductor integrated circuit is provided with the following elements: ground conductors separated into a plurality of routes on a semiconductor substrate; a first circuit for receiving an input signal from the outside; a second circuit for receiving an output from the first circuit; wherein a first ground conductor, one of the ground conductors separated into the plurality of routes, is used as a ground conductor only for the first circuit and the ground conductors other than the first ground conductor are used as ground conductors for circuits other than the first circuit.
  • the semiconductor integrated circuit may further comprise an output circuit for outputting an output signal to the outside, wherein one of the ground conductors separated into the plurality of routes is used exclusively for the output circuit.
  • a semiconductor integrated circuit is provided with the following elements: an input circuit for receiving an input signal from the outside; a succeeding-stage circuit connected to the input circuit; an internal circuit connected to the succeeding-stage circuit; an output circuit connected to the internal circuit for outputting an output signal to the outside; a power supply line connected to each of the circuits; a power supply terminal connected to the power supply line; a first ground conductor connected to the input and succeeding-stage circuits; a second ground conductor separated from the first ground conductor and connected to the output circuit; a third ground conductor separated from the ground conductor and connected to the output circuit; a first ground terminal connected to the first ground conductor; and a second ground terminal connected to the second ground conductor.
  • the power supply line is commonly connected to each of the circuits and the second and third ground conductors are formed in a common manner.
  • the semiconductor integrated circuit may comprise a third ground terminal connected to the third ground conductor, wherein the power supply line includes a first power supply line commonly connected to the input and internal circuits and a second power supply line separated from the first power supply line and connected to the output circuit, the power supply terminal includes a first power supply terminal connected to the first power supply line and a second power supply terminal connected to the second power supply line, and the second and third ground conductors are separated from each other.
  • the power supply terminals are respectively connected to ground terminals separated into a plurality of routes outside an integrated circuit chip.
  • the ground terminals are respectively connected to ground terminals separated into a plurality of routes outside an integrated circuit chip.
  • the input and succeeding-stage circuits are respectively provided with NMOS transistors formed on a p type well formed in a n-type semiconductor substrate, the first ground conductor is connected to a source region for the NMOS transistor comprising a n-type impurity diffused layer formed in the p type well, the second ground conductor is connected to a p type well electrode region comprising a p-type impurity diffused layer formed in said p type well, and a p-n junction diode formed between the p type well and the source region of said NMOS transistor exists between the second ground conductor and the first ground conductor.
  • another diode in a direction opposite the p-n junction diode is further provided between the second ground conductor and the first ground conductor.
  • a semiconductor integrated circuit is provided with the following elements: ground conductors separated into a plurality of routes on a semiconductor substrate; a plurality of first circuits for respectively receiving different input signal from the outside; and a plurality of second circuits respectively corresponding to the plurality of first circuits for receiving outputs therefrom, wherein a first ground conductor, one of the ground conductors separated into the plurality of routes is used as a ground conductor only for the plurality of first circuits and some of succeeding-stage circuits of the plurality of second circuits, and the ground conductors other than the first ground conductor are used as ground conductors for circuits other than the first and second circuits and remaining succeeding-stage circuits of the plurality of second circuits.
  • a semiconductor integrated circuit is provided with the following elements: a plurality of input circuits for respectively receiving different input signals from the outside; a plurality of succeeding-stage circuits respectively connected to the plurality of input circuits in a corresponding manner; an internal circuit connected to the succeeding-stage circuits; a plurality of output circuits connected to the internal circuit for respectively outputting output signals to the outside; a power supply line connected to each of the circuits; a power supply terminal connected to the power supply line; a first ground conductor connected to the plurality of input circuits and some of the plurality of succeeding-stage circuits; a second ground conductor separated from the first ground conductor and connected to the internal circuit and the rest of the plurality of succeeding-stage circuits; a third ground conductor separated from the first ground conductor and connected to the output circuits; a first ground terminal connected to the first ground conductor; and a second ground terminal connected to the second ground conductor.
  • some of the plurality of succeeding-stage circuits to which the first ground conductor is connected are CMOS inverter circuits, of the plurality of input circuits, the ones in the preceding stage of the CMOS inverter circuits are CMOS Schmitt circuits, and input signals received by the CMOS Schmitt circuits are placed in a high impedance state while the output circuits provide output signals.
  • the ones to which the second ground conductor is connected are CMOS inverter circuits.
  • the ones in the preceding stage of the CMOS inverter circuits are CMOS Schmitt circuits, and input signals input to the CMOS Schmitt circuits cause the CMOS Schmitt circuits to be low levels while the output circuits provide output signals.
  • FIG. 1 is a block diagram showing a structure of DRAM of a multibit configuration in a first embodiment of a semiconductor integrated circuit of the invention.
  • FIG. 2 is a circuit diagram showing one input buffer circuit and its peripheral circuit extracted from FIG. 1 and an external structure of an integrated circuit chip associated therewith.
  • FIG. 3 is a wave form chart showing in detail an example of potential changes of a /CAS signal, an output data Dout, a power supply line, a first ground conductor, a second ground conductor and an output node of an internal circuit in a hyper page mode of the DRAM of FIG. 1.
  • FIG. 4 is a circuit diagram showing an input buffer circuit for /WE input and its peripheral circuit of a DRAM of a multibit configuration in a second embodiment of a semiconductor integrated circuit of the invention and an external structure of an integrated circuit chip associated therewith.
  • FIG. 5 is a wave form chart showing in detail an example of potential changes of a /CAS signal, an output data Dout, a power supply line, a first ground conductor, a second ground conductor and an output node of an internal circuit in a hyper page mode of the DRAM of FIG. 4.
  • FIG. 6 is a block diagram showing a plurality of input buffer circuits and their peripheral circuits of a DRAM of a multibit configuration in a third embodiment of a semiconductor integrated circuit of the invention and an external structure of an integrated circuit chip associated therewith.
  • FIG. 7 is a block diagram showing a plurality of input buffer circuits and their peripheral circuits of a DRAM of a multibit configuration in a fourth embodiment of a semiconductor integrated circuit of the invention and an external structure of an integrated circuit chip associated therewith.
  • FIGS. 8A and 8B are views showing different examples of a connection between ground terminals (or power supply terminals) separated into a plurality of routes on a semiconductor integrated circuit chip of the invention and terminals outside the integrated circuit chip.
  • FIG. 9 is a view showing an example of a connection between a cross-sectional structure of a CMOS inverter for an input circuit and ground conductors separated into a plurality of routes in a DRAM of a multibit configuration in a fifth embodiment of a semiconductor integrated circuit of the invention.
  • FIG. 10 is a timing wave form chart showing a read operation in a fast page mode and a read operation in a hyper page mode in conventional DRAM of a multibit configuration.
  • FIG. 1 illustrates in a schematic block diagram a structure of DRAM of a multibit configuration in a first embodiment of a semiconductor integrated circuit of the invention.
  • a reference character 1 represents a power supply terminal to which a power source potential VDD is applied from the outside, 2a and 2b first and second ground terminals respectively to which a ground potential VSS is provided from the outside, 3 a /RAS terminal to which a /RAS (/Row Address Strobe) signal is input from the outside, 4 a /CAS terminal to which a /CAS is input from the outside, 5 a /WE terminal to which a /WE (/Write Enable) signal is input from the outside and 6 a /OE terminal to which a /OE (Output Enable) signal is input from the outside.
  • Reference characters 7 1 to 7 m are input/output terminals to which write data Din are input from the outside or from which data output Dout inside DRAM are output to the outside.
  • 8 1 to 8 n are address terminals to which address signals A0 to An are input from the outside.
  • a reference character 11 represents a /RAS buffer to which the /RAS signal is input, 12 a /CAS buffer to which the /CAS signal is input, 13 a /WE buffer to which the /WE signal is input, 14 a /OE buffer to which the /OE signal is input, 15 1 to 15 n row address buffers to which row address signals of the address signals A0 to An input from the address terminals 8 1 to 8 n are input, 16 1 to 16 n are column address buffers to which column address signals of the address signals A0 to An input from the address terminals 8 1 to 8 n are input and 17 1 to 17 m are Din buffers to which data Din input from the input/output terminals 7 1 to 7 m are input.
  • a reference character 20 represents a sense amplifier control circuit for producing a sense amplifier control signal based on the output of the /RAS buffer 11, 21 a row address buffer control circuit for producing a row address buffer control signal based on the output of the /RAS buffer, 22 a column address buffer control circuit for producing a column address buffer control signal based on the output of the /CAS buffer 12, 23 a Din buffer control circuit for producing a data input buffer control signal based on the outputs of the /RAS buffer 11, the /CAS buffer 12 and /WE buffer 13.
  • Reference characters 24 and 25 represent a predecoding row partial decoder and a row main decoder for decoding the outputs of the row address buffers 15 1 to 15 n .
  • a reference character 26 represents a memory cell array in which row selection is performed based on the output of the row decoder 25, and 27 a sense amplifier for detecting a reading potential from the memory cell array 26.
  • Reference characters 28 and 29 represent a predecoding column partial decoder and a column main decoder for decoding the outputs of the column address buffers 16 1 to 16 n .
  • a reference character 30 represents a DQ buffer inserted into a data line pair for performing input/output of data with a column selected and controlled based on the output of the column decoder 29, and 31 a DQ buffer control circuit controlled based on the output of the /CAS buffer 12 for controlling the DQ buffer 30.
  • a reference character 32 represents a data input control circuit provided between the DQ buffer 30 and the Din buffers 17 1 to 17 m and controlled based on the output of the /WE buffer 13 for outputting the data inputs Din of the Din buffer 17 1 to 17 m to the DQ buffer 30.
  • a reference character 33 represents a data output buffer provided between the DQ buffer 30 and the input/output terminals 7 1 to 7 m and controlled based on the outputs of the /WE buffer 13 and the /OE buffer 14 for outputting the output of the DQ buffer 30 as output data Dout to the input/output terminals 7 1 to 7 m .
  • FIG. 2 illustrates one of the input buffer circuits and its peripheral circuit shown in FIG. 1 and the external structure of an integrated circuit chip associated therewith.
  • a reference character 10 represents an integrated circuit chip section on a semiconductor substrate, 41 an external power source outside the integrated circuit chip, 42 an external buffer circuit for supplying a /WE signal outside the integrated circuit chip, 431 to 434 parasitic impedance in wiring from the external power source 41 to the integrated circuit chip section 10.
  • an input buffer circuit 131 for receiving an input signal from the outside may be constituted of a CMOS Schmitt circuit.
  • a reference character 132 represents a succeeding-stage circuit constituted of, for instance, a CMOS inverter circuit, connected to the output of the input buffer circuit 131, and 133 a third stage circuit constituted of, for instance, a CMOS inverter circuit, connected to the output of the succeeding-stage circuit 132.
  • These circuits 132 and 133 constitute a portion of the internal circuit.
  • an output buffer circuit 134 is connected for outputting an output signal to the outside.
  • the input buffer CMOS Schmitt circuit 131 is connected between a power source potential supply node and a ground potential supply node in series.
  • the input buffer CMOS Schmitt circuit 131 comprises a PMOS transistor P1 and NMOS transistors N1 and N2 whose respective gates are commonly connected and a NMOS transistor N3 connected to the NMOS transistor N1 in parallel.
  • the CMOS inverter circuit 132 for the succeeding-stage circuit is connected between the power source potential supply node and the ground potential supply node in series.
  • the CMOS inverter circuit 132 comprises a PMOS transistor P2 and a NMOS transistor N4 whose respective gates are commonly connected.
  • the CMOS inverter circuit 133 for the third stage circuit is connected between the power source potential supply node and the ground potential supply node in series.
  • the CMOS inverter circuit 133 comprises a PMOS transistor P3 and a NMOS transistor N4.
  • a power supply line 100 is connected between the power supply terminal 1 and the power source potential supply node of each of the circuits, a first ground conductor 101 (i.e., a ground conductor exclusively for the input buffer 131) is connected between a first ground terminal 2a and the ground potential supply node of the input buffer 131, and a second ground conductor 102 separated from the first ground conductor 101 is connected between a second ground terminal 2b and the ground potential supply node of the internal circuit (inverter circuits 132 and 133).
  • a first ground conductor 101 i.e., a ground conductor exclusively for the input buffer 131
  • a second ground conductor 102 separated from the first ground conductor 101 is connected between a second ground terminal 2b and the ground potential supply node of the internal circuit (inverter circuits 132 and 133).
  • a reference character 103 represents a third ground conductor connected to the ground potential supply node of the output buffer 134.
  • the third ground conductor 103 is separated from the first ground conductor 101.
  • the third ground conductor 103 is commonly formed with the second ground conductor 102.
  • the input buffer 131 Upon receiving the /WE signal, the input buffer 131 provides its inversion signal WE to a node M2. Upon receiving the WE signal, the succeeding-stage circuit 132 outputs its inversion signal /WE to a node M3. Upon receiving the inversion signal /WE, the third stage circuit 133 outputs its inversion signal WE to a node M4 and controls the operation of the circuit (not shown) in the next stage.
  • output data Dout is output in the active period of a /CAS signal and in the non-active period the output is placed in a high impedance state.
  • output data Dout is switched in synchronization with the leading edge of the /CAS signal. Changing of the output data in the hyper page mode is carried out between the high level "H” and the low level "L".
  • FIG. 3 shows in detail an example of changes in the /CAS signal in the hyper page mode, the output data Dout, the potential VDD of the power supply line 100, the potential VSS1 of the first ground conductor 101, the potential VSS2 of the second ground conductor 102 and the potential of the node M3 of the internal circuit.
  • Dout may be output at high level "1". Then, it is assumed that when the leading edge of the /CAS signal (trailing edge in this example) is received, Dout changes to a low level "0".
  • the ground conductor 101 exclusively for the input buffers 131, it is possible to suppress fluctuations in potential differences between the signal input node and the ground potential supply node of the input buffer circuit 131 (that is, a voltage margin with regard to the external input signal is advanced). Therefore, especially in the DRAM of a multibit structure, even when output noises (fluctuations in the power source potential or the ground potential) are large following a change in output data, the input buffer circuit will be prevented from malfunctioning due to the output noises.
  • the semiconductor integrated circuit of the first embodiment is provided with ground conductors separated into a plurality of routes on a semiconductor substrate, a first circuit for receiving an input signal from the outside and a second circuit for receiving the output of the first circuit.
  • the first ground conductor, one of the ground conductors separated into the plurality of routes, is used as a ground conductor only for the first circuit, and those other than the first ground conductor are used as ground conductors for the circuits other than the first circuit.
  • the /WE signal is set in a high impedance state.
  • FIG. 3 there is a possibility that while output data Dout changes, the potential of the output node M3 of the succeeding-stage circuit 132 of the input buffer circuit 131 for /WE signal input may greatly change, leading to malfunction of the third stage inverter circuit 133. This will now be described in detail.
  • the /WE signal When the /WE signal is in a high impedance state, the electric charge of the output node M2 of the CMOS Schmitt circuit 131 is discharged to the first ground conductor 101. Then, the potential of the node M2 becomes equal to the potential VSS1 of the first ground conductor 101 and the potential of the output node M3 of the CMOS inverter circuit becomes a "H" level.
  • the potential of the signal input node of the CMOS inverter circuit 132 is equal to the potential VSS1 of the first ground conductor 101, the potential of the ground potential supply node is equal to the potential VSS2 of the second ground conductor 102 and thus, the CMOS inverter circuit is driven between the two ground potentials VSS1 and VSS2 separated from each other.
  • the potential VSS2 of the second ground conductor 102 will temporarily float up while no changes occur in the potential of the output node M2 of the CMOS Schmitt circuit 131.
  • the circuit threshold value will substantially fall and the potential of its output node M3 will temporarily increase.
  • FIG. 4 illustrates an input buffer circuit for /WE input and the peripheral circuit of a DRAM of a multibit structure in a second embodiment of the semiconductor integrated circuit of the invention and an external structure of an integrated circuit chip associated therewith.
  • the circuit structure shown in FIG. 4 is different from the circuit structure shown in FIG. 2 in that the first ground conductor 101 is connected to the input buffer circuit 131 and the succeeding-stage circuit 132 and the second ground conductor 102 is connected from the succeeding-stage circuit 132 to the internal circuits in the succeeding stages (including the third stage circuit 133 and the output buffer circuit 134). Others are substantially the same and the same reference numerals are used for the same parts as in FIG. 2.
  • FIG. 5 shows in detail an example of changes in a /CAS signal, output data Dout, the potential VDD of the power supply line 100, the potential VSS1 of the first ground conductor 101, the potential VSS2 of the second ground conductor 102 and the potential of the node M3 of the internal circuit, in the hyper page mode of the DRAM having the circuit structure as shown in FIG. 4.
  • the operation of the circuit shown in FIG. 4 is (1) basically similar thereto and as described by referring to FIG. 3, the voltage margin with regard to the external input signal has been improved, and (2) the operation of the succeeding-stage circuit 132 to which the first ground conductor 101 is connected is different therefrom, a glitch is prevented from being produced in the output node M3 of the succeeding-stage circuit 132 during changing of the output and thus, malfunction of the internal circuit is prevented.
  • a /WE signal is set in a high impedance state. While the /WE signal is set in the high impedance state, the electric charge of the output node M2 of the input buffer circuit (CMOS Schmitt circuit) 131 is discharged to the first ground conductor 101, the potential of the output node M2 becomes equal to the potential VSS1 of the first ground conductor 101 and the potential of the output node M3 of the succeeding-stage circuit (CMOS inverter circuit) becomes a "H" level.
  • the potential of the signal input node and the potential of the ground potential supply node of the succeeding-stage circuit 132 are respectively equal to the potential VSS1 of the first ground conductor 101.
  • FIG. 6 illustrates a plurality of input buffer circuits and their peripheral circuits of a DRAM of a multibit structure in a third embodiment of the semiconductor integrated circuit of the invention and an external structure of an integrated circuit chip associated therewith.
  • the DRAM of the third embodiment is provided with a plurality of input circuits (e.g., CMOS Schmitt circuit) K4, K6 and K8 for receiving different input signals from the outside, a plurality of succeeding-stage circuits (e.g., CMOS inverter circuit) K5, K7 and K9 connected to the plurality of input circuits in a corresponding manner, an internal circuit K10 connected to the succeeding-stage circuits, a plurality of output circuits K11 connected to the internal circuit for outputting output signals to the outside, a power supply line 100 connected to each of the circuits, a power supply terminal 1 connected to the power supply line, a first ground conductor 101 connected to the plurality of input circuits and some of the plurality of succeeding-stage circuits, a second ground conductor 102 separated from the first ground conductor and connected to the internal circuit and the rest of the plurality of succeeding-stage circuits, a third ground conductor 103 separated from the first ground conductor and connected to the output circuits, a first
  • the structure of the circuit shown in FIG. 6 comprises a first circuit section in which the first and second ground conductors 101 and 102 are connected respectively to the input circuit and the succeeding-stage circuit as shown in FIG. 2 and a second circuit section in which the first ground conductor 101 is commonly connected to the input circuit and the succeeding-stage circuit as shown in FIG. 4.
  • reference numerals 421 to 423 represent external buffer circuits outside the integrated circuit chip, 431 to 436 parasitic impedance in a wiring from the external power source 41 to the integrated circuit chip 10, K4, K6 and K8 input circuits, K5, K7, K9 succeeding-stage circuits, K10 an internal circuit and K11 output circuits.
  • K4 K6 and K8 input circuits
  • K10 an internal circuit and K11 output circuits.
  • the same reference numerals as in FIGS. 2 and 4 are used.
  • an input signal (e.g., /RAS) at a low level during outputting of an output signal from the output circuit K11 is input to the first circuit section while an input signal (e.g., /WE) placed in a high impedance state during outputting of the output signal from the output circuit K11 is input to the second circuit section.
  • an input signal e.g., /RAS
  • an input signal e.g., /WE
  • the output node of its input circuit is at a power source potential VDD.
  • VDD power source potential
  • the potential of the output node of the input circuit will not change. Almost no changes will occur in the potential VSS1 of the first ground conductor, either.
  • the potential of its signal input node is equal to the power source potential VDD and the potential of the ground potential supply node is equal to the potential VSS2 of the second ground conductor 102.
  • the power source potential VDD and the potential VSS2 of the second ground conductor 102 fluctuate in same phase, malfunction will be prevented.
  • the number of inversion circuits contained in the circuit (input buffer circuit) up to the internal circuit to be prevented from malfunctioning due to output noises is an odd number, the operation as described above will be performed.
  • the DRAM of the third embodiment is provided with ground conductors separated into a plurality of routes on a semiconductor substrate, a plurality of first circuits for respectively receiving different input signals from the outside and a plurality of second circuits for receiving outputs from the plurality of first circuits in a corresponding manner.
  • a first ground conductor one of the ground conductors separated into the plurality of routes, is used as a ground conductor only for the plurality of first circuits and some of the succeeding-stage circuits of the plurality of second circuits.
  • the ground conductors other than the first ground conductor are used as ground conductors for the circuits other than the first an second circuits and the rest of the succeeding-stage circuits of the plurality of second circuits.
  • FIG. 7 illustrates a plurality of input buffer circuits and their peripheral circuits of a DRAM of a multibit structure in a fourth embodiment of the semiconductor integrated circuit of the invention and an external structure of an integrated circuit chip associated therewith.
  • the DRAM of the fourth embodiment is different from that of the third embodiment described by referring to FIG. 6 in that (1) the power supply line 100 comprises a first power supply line 100a commonly connected to the input circuits K4 and K8, the succeeding circuits K5 and K9 and the internal circuit K10 and a second power supply line 100b separated from the first power supply line 100a and connected to the output circuit K11, (2) the power supply terminal 1 comprises a first power supply terminal 1a connected to the first power supply line 100a and a second power supply terminal 1b connected to the second power supply line 100b and (3) the second and third ground conductors 102 and 103 are separated, the ground conductor 103 is used exclusively for the output circuit K11 and a third ground terminal 2c connected to the third ground conductor 103 is further provided.
  • 437 and 438 represent impedance parasitic in a wiring from the external power source 41 to the integrated circuit chip 10 and 439 parasitic impedance from the output circuit to an external load.
  • the DRAM of the fourth embodiment since the power supply line 100b exclusively for the output circuit and the ground conductor 103 are separated from the power supply line 100a and the ground conductors 101 and 102 for the other circuits, it will be difficult for fluctuations to occur in the potentials of the power supply line and the ground conductors for the other circuits during changing of the output.
  • FIGS. 8A and 8B respectively show different examples of a connection between ground terminals separated into a plurality of routes (or power supply terminals) on the semiconductor integrated circuit chip of the invention and terminals outside the integrated circuit chip.
  • ground pads (or power pads) 2a, 2b and 2c separated into three routes on the integrated circuit chip 10 are shown to be commonly connected to one ground terminal section (or a power supply terminal section) 71 on, for instance, a lead frame outside the integrated circuit chip via a bonding wire 72.
  • the ground pads (or power pads) 2a, 2b and 2c separated into three routes on the integrated circuit chip 10 are shown to be differently connected to the ground terminals of three routes (or power supply terminals) 73 t0 75 via the bonding wire 72.
  • FIG. 9 shows an example of a connection between the cross-sectional structure of a CMOS inverter for an input circuit and, for instance, ground conductors of two routes in DRAM of a multibit structure in a fifth embodiment of the semiconductor integrated circuit of the invention.
  • a reference character 80 represents a n-type semiconductor substrate, 81 a p type well formed in the substrate, and 82 a n type well formed in the p type well.
  • Reference characters 83 and 84 represent source and drain regions for a PMOS transistor constituted of a p+ type impurity diffused layer formed in a portion of the surface layer section of the n type well 82, 85 a n type well electrode region constituted of a n+ type impurity diffused layer formed in a portion of the surface layer section of the n type well 82 and 86 a gate electrode for a PMOS transistor formed on a channel region between the source and the drain of the PMOS transistor via a gate insulated film.
  • Reference characters 87 and 88 represent source and drain regions for a NMOS transistor constituted of a n+ type impurity diffused layer formed in a portion of the surface layer section of the p type well 81, 89 a p type well electrode region constituted of a p+ type impurity diffused layer formed in a portion of the surface layer section of the p type well 81 and 90 a gate electrode for a NMOS transistor formed on a channel region between the source and the drain of the NMOS transistor via a gate insulated film.
  • External input signals are commonly input to the gate electrode 86 for the PMOS transistor and the gate electrode 90 for the NMOS transistor and the drain 84 for the PMOS transistor and the drain 88 for the NMOS transistor are commonly connected to the signal input node of the succeeding-stage circuit.
  • a power source potential VDD is supplied to the source region 83 for the PMOS transistor and the n type well electrode region 85, the source region 87 for the NMOS transistor is connected to the first ground conductor 101 and the p type well electrode region 89 is connected to the second ground conductor 102.
  • a p-n junction diode 91 formed between the p type well 81 and the source region 87 for the NMOS transistor exists between the second ground conductor 102 and the first ground conductor 101.
  • another diode 92 is provided between the second ground conductor 102 and the first ground conductor 101 in a direction opposite the p-n junction diode 91. This enables the diode 92 to be turned ON when the potential VSS2 of the second ground conductor 102 falls and its potential difference from the first ground conductor exceeds the forward falling voltage V F of the diode 92. In this manner, while the potential VSS1 of the first ground conductor also falls, it is possible to suppress a potential difference below V F between the first ground conductor 101 and the second ground conductor 102.
  • the semiconductor integrated circuit is provided, wherein it is possible to prevent malfunction of the internal circuit due to output noises accompanying changes in the output data.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
US08/706,394 1995-09-01 1996-08-30 Semiconductor integrated circuit Expired - Lifetime US5914505A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7225387A JPH0973780A (ja) 1995-09-01 1995-09-01 半導体集積回路
JP7-225387 1995-09-01

Publications (1)

Publication Number Publication Date
US5914505A true US5914505A (en) 1999-06-22

Family

ID=16828569

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/706,394 Expired - Lifetime US5914505A (en) 1995-09-01 1996-08-30 Semiconductor integrated circuit

Country Status (4)

Country Link
US (1) US5914505A (ja)
JP (1) JPH0973780A (ja)
KR (1) KR100224051B1 (ja)
TW (1) TW345737B (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6057729A (en) * 1997-06-17 2000-05-02 Nec Corporation Power circuit
US6218707B1 (en) * 1997-07-23 2001-04-17 Stmicroelectronics S.R.L. Leakage-free integrated electronic switch
US20020171079A1 (en) * 1997-07-14 2002-11-21 Erez Braun Microelectronic components and electronic networks comprising dna
US20030203394A1 (en) * 1998-05-04 2003-10-30 Yoav Eichen Detection of a target in a sample
US20040033626A1 (en) * 1998-10-27 2004-02-19 Erez Braun Method for gold deposition
US20060211136A1 (en) * 1999-10-27 2006-09-21 Technion Research And Development Foundation Ltd. Method for gold deposition
US20100074043A1 (en) * 2008-09-19 2010-03-25 Khil-Ohk Kang Semiconductor device
US20120043595A1 (en) * 2010-08-19 2012-02-23 Dong-Ryul Chang Capacitor device and method of fabricating the same
US20220188589A1 (en) * 2019-12-12 2022-06-16 Au Optronics Corporation Integrated circuit, wireless communication card and wiring structure of identification mark

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013029963A (ja) * 2011-07-28 2013-02-07 New Japan Radio Co Ltd 定電圧出力回路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111069A (en) * 1990-08-27 1992-05-05 Dallas Semiconductor Corporation Layout of integrated circuit with very large transistors
US5144161A (en) * 1990-03-16 1992-09-01 Oki Electric Industry Co., Ltd. Logic circuit for switching noise reduction
US5293559A (en) * 1991-08-01 1994-03-08 Samsung Electronics Co., Ltd. Semiconductor memory device having netlike power supply lines
US5394008A (en) * 1992-06-30 1995-02-28 Hitachi, Ltd. Semiconductor integrated circuit device
US5608594A (en) * 1992-04-14 1997-03-04 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit with surge-protected output MISFET's

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5144161A (en) * 1990-03-16 1992-09-01 Oki Electric Industry Co., Ltd. Logic circuit for switching noise reduction
US5111069A (en) * 1990-08-27 1992-05-05 Dallas Semiconductor Corporation Layout of integrated circuit with very large transistors
US5293559A (en) * 1991-08-01 1994-03-08 Samsung Electronics Co., Ltd. Semiconductor memory device having netlike power supply lines
US5608594A (en) * 1992-04-14 1997-03-04 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit with surge-protected output MISFET's
US5394008A (en) * 1992-06-30 1995-02-28 Hitachi, Ltd. Semiconductor integrated circuit device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6057729A (en) * 1997-06-17 2000-05-02 Nec Corporation Power circuit
US20020171079A1 (en) * 1997-07-14 2002-11-21 Erez Braun Microelectronic components and electronic networks comprising dna
US6946675B2 (en) 1997-07-14 2005-09-20 Technion Research & Development Foundation Ltd. Microelectronic components and electronic networks comprising DNA
US20050214806A1 (en) * 1997-07-14 2005-09-29 Erez Braun Microelectronic components and electronic networks comprising DNA
US6218707B1 (en) * 1997-07-23 2001-04-17 Stmicroelectronics S.R.L. Leakage-free integrated electronic switch
US20030203394A1 (en) * 1998-05-04 2003-10-30 Yoav Eichen Detection of a target in a sample
US7851149B2 (en) 1998-10-27 2010-12-14 Erez Braun Method for gold deposition
US20040033626A1 (en) * 1998-10-27 2004-02-19 Erez Braun Method for gold deposition
US7056748B1 (en) 1998-10-27 2006-06-06 Technion Research And Development Foundation Ltd. Method for gold deposition
US20060211136A1 (en) * 1999-10-27 2006-09-21 Technion Research And Development Foundation Ltd. Method for gold deposition
US7364920B2 (en) 1999-10-27 2008-04-29 Technion Research And Development Foundation Ltd. Method for gold deposition
US20100074043A1 (en) * 2008-09-19 2010-03-25 Khil-Ohk Kang Semiconductor device
US7936632B2 (en) * 2008-09-19 2011-05-03 Hynix Semiconductor Inc. Semiconductor device including an internal circuit receiving two different power supply sources
US20120043595A1 (en) * 2010-08-19 2012-02-23 Dong-Ryul Chang Capacitor device and method of fabricating the same
US8749022B2 (en) * 2010-08-19 2014-06-10 Samsung Electronics Co., Ltd. Capacitor device and method of fabricating the same
US20220188589A1 (en) * 2019-12-12 2022-06-16 Au Optronics Corporation Integrated circuit, wireless communication card and wiring structure of identification mark
US11687757B2 (en) * 2019-12-12 2023-06-27 Au Optronics Corporation Integrated circuit, wireless communication card and wiring structure of identification mark

Also Published As

Publication number Publication date
TW345737B (en) 1998-11-21
KR970017607A (ko) 1997-04-30
KR100224051B1 (ko) 1999-10-15
JPH0973780A (ja) 1997-03-18

Similar Documents

Publication Publication Date Title
KR950010621B1 (ko) 반도체 기억장치
US4899066A (en) OR-type CMOS logic circuit with fast precharging
US6133752A (en) Semiconductor integrated circuit having tri-state logic gate circuit
JPH0143464B2 (ja)
US4692638A (en) CMOS/NMOS decoder and high-level driver circuit
US4654831A (en) High speed CMOS current sense amplifier
US5200921A (en) Semiconductor integrated circuit including P-channel MOS transistors having different threshold voltages
JPH04355298A (ja) 高い出力利得を得るデータ出力ドライバー
KR100224051B1 (ko) 반도체 집적회로
US20080001656A1 (en) Semiconductor integrated circuit
US5446700A (en) Decoder circuit having CMOS inverter circuits
JPS62183624A (ja) Ｅｃｌトランジスタ論理回路からｆｅｔ論理回路を駆動するためのインターフェース回路
US5237536A (en) Semiconductor memory device having split operation and capable of reducing power supply noise
US5805506A (en) Semiconductor device having a latch circuit for latching data externally input
US5469385A (en) Output buffer with boost from voltage supplies
US4902911A (en) Semiconductor integrated circuit having a built-in power voltage generator
US6172527B1 (en) Output circuit capable of reducing feedthrough current
US5804988A (en) Logic and level conversion circuit
EP0477758B1 (en) Semiconductor integrated circuit including P-channel MOS transistors having different threshold voltages
JP3159404B2 (ja) 出力ドライバ回路
JP2000261304A (ja) 半導体装置
JPH0677806A (ja) 半導体記憶装置の出力回路
US5825703A (en) Semiconductor memory device having p-channel field effect transistor to drive word line
JP2001093285A (ja) 半導体記憶装置
JP3055233B2 (ja) 入力バッファ回路

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HISADA, TOSHIKI;KOINUMA, HIROYUKI;REEL/FRAME:008195/0193

Effective date: 19960822

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12