WO2003100854A3 - Elektronisches bauelement-modul und verfahren zu dessen herstellung - Google Patents

Elektronisches bauelement-modul und verfahren zu dessen herstellung Download PDF

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Publication number
WO2003100854A3
WO2003100854A3 PCT/DE2003/001612 DE0301612W WO03100854A3 WO 2003100854 A3 WO2003100854 A3 WO 2003100854A3 DE 0301612 W DE0301612 W DE 0301612W WO 03100854 A3 WO03100854 A3 WO 03100854A3
Authority
WO
WIPO (PCT)
Prior art keywords
projections
production
electronic component
connection
component module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2003/001612
Other languages
English (en)
French (fr)
Other versions
WO2003100854A2 (de
Inventor
Marcel Heerman
Puymbroeck Jozef Van
Eric Beyne
Bart Vandevelde
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to AU2003232635A priority Critical patent/AU2003232635A1/en
Publication of WO2003100854A2 publication Critical patent/WO2003100854A2/de
Anticipated expiration legal-status Critical
Publication of WO2003100854A3 publication Critical patent/WO2003100854A3/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/091—Locally and permanently deformed areas including dielectric material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

Ein Anschluss-Substrat für mindestens ein elektronisches Bauelement besitzt einen flachen Substratkörper , in dessen ebener Oberfläche jeweils Innenkontakt-Höcker (3) zur Flip-Chip-Kontaktierung eines Bauelements und ggf. Aussenkontakt-Höcker (9) zum Anschluss an eine Leiterplatte jeweils durch Teilabtragung oder Verformung (2; 8) vertieft angeordnet sind. Durch die Herstellung dieser Kontakt-Höcker im Heisspräge-Verfahren bzw. mittels Laserabtragung können sie sehr klein und in einem engeren Raster als bisherige Chip-Anschlüsse hergestellt werden.
PCT/DE2003/001612 2002-05-24 2003-05-19 Elektronisches bauelement-modul und verfahren zu dessen herstellung Ceased WO2003100854A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003232635A AU2003232635A1 (en) 2002-05-24 2003-05-19 Electronic component module and method for the production thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10223203.2 2002-05-24
DE10223203A DE10223203B4 (de) 2002-05-24 2002-05-24 Elektronisches Bauelement-Modul und Verfahren zu dessen Herstellung

Publications (2)

Publication Number Publication Date
WO2003100854A2 WO2003100854A2 (de) 2003-12-04
WO2003100854A3 true WO2003100854A3 (de) 2005-01-06

Family

ID=29414141

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001612 Ceased WO2003100854A2 (de) 2002-05-24 2003-05-19 Elektronisches bauelement-modul und verfahren zu dessen herstellung

Country Status (3)

Country Link
AU (1) AU2003232635A1 (de)
DE (1) DE10223203B4 (de)
WO (1) WO2003100854A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100555706B1 (ko) * 2003-12-18 2006-03-03 삼성전자주식회사 미세 솔더볼 구현을 위한 ｕｂｍ 및 이를 이용한 플립칩패키지 방법
US20080171181A1 (en) * 2007-01-11 2008-07-17 Molex Incorporated High-current traces on plated molded interconnect device
US8829663B2 (en) 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through
CN104380432A (zh) 2012-03-30 2015-02-25 Msg里松格莱斯股份公司 半导体器件和用于制造类玻璃层的方法
US8963335B2 (en) 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814295A (en) * 1986-11-26 1989-03-21 Northern Telecom Limited Mounting of semiconductor chips on a plastic substrate
WO1996009646A1 (de) * 1994-09-23 1996-03-28 Siemens N.V. Polymer stud grid array
US6002590A (en) * 1998-03-24 1999-12-14 Micron Technology, Inc. Flexible trace surface circuit board and method for making flexible trace surface circuit board
US6060665A (en) * 1998-03-16 2000-05-09 Lucent Technologies Inc. Grooved paths for printed wiring board with obstructions
GB2349014A (en) * 1999-03-19 2000-10-18 Ibm Method for forming an electronic structure
WO2001082372A1 (de) * 2000-04-20 2001-11-01 Siemens Aktiengesellschaft Polymer stud grid array mit durchkontaktierungen und verfahren zur herstellung eines substrats für ein derartiges polymer stud grid array
EP1106040B1 (de) * 1998-07-10 2002-03-27 Siemens S.A. Verfahren zur herstellung von verdrahtungen mit elektrisch leitenden querverbindungen zwischen ober- und unterseite eines substrats sowie verdrahtung mit derartigen querverbindungen
WO2002045163A2 (de) * 2000-11-29 2002-06-06 Siemens Dematic Ag Verfahren zur herstellung von halbleitermodulen sowie nach dem verfahren hergestelltes modul

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998027589A1 (en) * 1996-12-19 1998-06-25 Telefonaktiebolaget Lm Ericsson (Publ) Flip-chip type connection with elastic contacts
DE10059176C2 (de) * 2000-11-29 2002-10-24 Siemens Ag Zwischenträger für ein Halbleitermodul, unter Verwendung eines derartigen Zwischenträgers hergestelltes Halbleitermodul sowie Verfahren zur Herstellung eines derartigen Halbleitermoduls

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814295A (en) * 1986-11-26 1989-03-21 Northern Telecom Limited Mounting of semiconductor chips on a plastic substrate
WO1996009646A1 (de) * 1994-09-23 1996-03-28 Siemens N.V. Polymer stud grid array
US6060665A (en) * 1998-03-16 2000-05-09 Lucent Technologies Inc. Grooved paths for printed wiring board with obstructions
US6002590A (en) * 1998-03-24 1999-12-14 Micron Technology, Inc. Flexible trace surface circuit board and method for making flexible trace surface circuit board
EP1106040B1 (de) * 1998-07-10 2002-03-27 Siemens S.A. Verfahren zur herstellung von verdrahtungen mit elektrisch leitenden querverbindungen zwischen ober- und unterseite eines substrats sowie verdrahtung mit derartigen querverbindungen
GB2349014A (en) * 1999-03-19 2000-10-18 Ibm Method for forming an electronic structure
WO2001082372A1 (de) * 2000-04-20 2001-11-01 Siemens Aktiengesellschaft Polymer stud grid array mit durchkontaktierungen und verfahren zur herstellung eines substrats für ein derartiges polymer stud grid array
WO2002045163A2 (de) * 2000-11-29 2002-06-06 Siemens Dematic Ag Verfahren zur herstellung von halbleitermodulen sowie nach dem verfahren hergestelltes modul

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CHRISTENSEN C ET AL: "WAFER THROUGH-HOLE INTERCONNECTIONS WITH HIGH VERTICAL WIRING DENSITIES", IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY: PART A, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 19, no. 4, 1 December 1996 (1996-12-01), pages 516 - 521, XP000638749, ISSN: 1070-9886 *

Also Published As

Publication number Publication date
AU2003232635A1 (en) 2003-12-12
DE10223203B4 (de) 2004-04-01
DE10223203A1 (de) 2003-12-04
WO2003100854A2 (de) 2003-12-04

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