WO2004100259A3 - Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements - Google Patents

Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements Download PDF

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Publication number
WO2004100259A3
WO2004100259A3 PCT/EP2004/003376 EP2004003376W WO2004100259A3 WO 2004100259 A3 WO2004100259 A3 WO 2004100259A3 EP 2004003376 W EP2004003376 W EP 2004003376W WO 2004100259 A3 WO2004100259 A3 WO 2004100259A3
Authority
WO
WIPO (PCT)
Prior art keywords
semi
conductor component
conductor
production
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2004/003376
Other languages
English (en)
French (fr)
Other versions
WO2004100259A2 (de
Inventor
Anton Mauder
Bernd Gutsmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
EUPEC GmbH
Original Assignee
Infineon Technologies AG
EUPEC GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, EUPEC GmbH filed Critical Infineon Technologies AG
Publication of WO2004100259A2 publication Critical patent/WO2004100259A2/de
Publication of WO2004100259A3 publication Critical patent/WO2004100259A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

Halbleiterbauelement und Verfahren zum Herstellen eines solchen Halbleiterbauelements. Das Halbleiterbauelement umfasst ein Substrat (3), auf dem ein oder mehrere Halbleiterchips (1, 2) angeordnet and kontaktiert sind. Auf einer isolierenden Maskierung (8), die Durchgangsöffnungen (12) zu Anschlussstellen (19) auf dem Substrat und/oder der Halbleiterchips (1) aufweist, ist eine strukturierte Leiterschicht aufgebracht, die sich durch die Durchgangsöffnungen (12) zu den Anschlussstellen (19) erstreckende integrale Fortsätze aufweist.
PCT/EP2004/003376 2003-05-09 2004-03-31 Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements Ceased WO2004100259A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10320877.1 2003-05-09
DE10320877A DE10320877A1 (de) 2003-05-09 2003-05-09 Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements

Publications (2)

Publication Number Publication Date
WO2004100259A2 WO2004100259A2 (de) 2004-11-18
WO2004100259A3 true WO2004100259A3 (de) 2005-03-31

Family

ID=33426721

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/003376 Ceased WO2004100259A2 (de) 2003-05-09 2004-03-31 Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements

Country Status (2)

Country Link
DE (1) DE10320877A1 (de)
WO (1) WO2004100259A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004061907A1 (de) * 2004-12-22 2006-07-13 Siemens Ag Halbleitermodul mit geringer thermischer Belastung
DE102005007373B4 (de) * 2005-02-17 2013-05-29 Infineon Technologies Ag Leistungshalbleiterbaugruppe
DE102005063532B3 (de) 2005-02-17 2022-03-10 Infineon Technologies Ag Leistungshalbleiterbaugruppe
DE102005010308B4 (de) * 2005-03-03 2017-07-27 First Sensor Microelectronic Packaging Gmbh Verfahren zur Herstellung von Chips mit lötfähigen Anschlüssen auf der Rückseite
DE102005011652B4 (de) * 2005-03-14 2007-06-14 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements
DE102007046969B3 (de) * 2007-09-28 2009-04-02 Siemens Ag Elektronische Schaltung aus Teilschaltungen und Verfahren zu deren Herstellung und demgemäßer Umrichter oder Schalter
DE102008058003B4 (de) 2008-11-19 2012-04-05 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleitermoduls und Halbleitermodul

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
DE9109295U1 (de) * 1991-04-11 1991-10-10 Export-Contor Außenhandelsgesellschaft mbH, 8500 Nürnberg Elektronische Schaltungsanordnung
EP0465197A2 (de) * 1990-07-02 1992-01-08 General Electric Company Dielektrische Mehrschichtstruktur
EP0465195A2 (de) * 1990-07-02 1992-01-08 General Electric Company Mehrschichtverbindungsverfahren hoher Dichte und Struktur mit thermoplastischen Klebern mit aufeinanderfolgenden abnehmenden Tg's
US6541378B1 (en) * 2001-11-06 2003-04-01 Lockheed Martin Corporation Low-temperature HDI fabrication

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules
US6876056B2 (en) * 2001-04-19 2005-04-05 Interuniversitair Microelektronica Centrum (Imec) Method and system for fabrication of integrated tunable/switchable passive microwave and millimeter wave modules

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
EP0465197A2 (de) * 1990-07-02 1992-01-08 General Electric Company Dielektrische Mehrschichtstruktur
EP0465195A2 (de) * 1990-07-02 1992-01-08 General Electric Company Mehrschichtverbindungsverfahren hoher Dichte und Struktur mit thermoplastischen Klebern mit aufeinanderfolgenden abnehmenden Tg's
DE9109295U1 (de) * 1991-04-11 1991-10-10 Export-Contor Außenhandelsgesellschaft mbH, 8500 Nürnberg Elektronische Schaltungsanordnung
US6541378B1 (en) * 2001-11-06 2003-04-01 Lockheed Martin Corporation Low-temperature HDI fabrication

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
FILLION R A ET AL: "STATUS AND UPDATE ON THE GE HDI MULTICHIP MODULE TECHNOLOGY", WESCON TECHNICAL PAPERS, WESTERN PERIODICALS CO. NORTH HOLLYWOOD, US, vol. 34, 1 November 1990 (1990-11-01), pages 733 - 738, XP000227948 *
FISHER R ET AL: "High frequency, low cost, power packaging using thin film power overlay technology", APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, 1995. APEC '95. CONFERENCE PROCEEDINGS 1995., TENTH ANNUAL DALLAS, TX, USA 5-9 MARCH 1995, NEW YORK, NY, USA,IEEE, US, 5 March 1995 (1995-03-05), pages 12 - 17, XP010147591, ISBN: 0-7803-2482-X *
HAHN R ET AL: "High power multichip modules employing the planar embedding technique and microchannel water heat sinks", SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, 1997. SEMI-THERM XIII., THIRTEENTH ANNUAL IEEE AUSTIN, TX, USA 28-30 JAN. 1997, NEW YORK, NY, USA,IEEE, US, 28 January 1997 (1997-01-28), pages 49 - 56, XP010211403, ISBN: 0-7803-3793-X *

Also Published As

Publication number Publication date
DE10320877A1 (de) 2004-12-09
WO2004100259A2 (de) 2004-11-18

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