WO2010143376A1 - Dispositif à semi-conducteurs et procédé de fabrication de celui-ci - Google Patents

Dispositif à semi-conducteurs et procédé de fabrication de celui-ci Download PDF

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Publication number
WO2010143376A1
WO2010143376A1 PCT/JP2010/003686 JP2010003686W WO2010143376A1 WO 2010143376 A1 WO2010143376 A1 WO 2010143376A1 JP 2010003686 W JP2010003686 W JP 2010003686W WO 2010143376 A1 WO2010143376 A1 WO 2010143376A1
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electrode
barrier metal
layer
film
metal wiring
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Japanese (ja)
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庭山雅彦
内田正雄
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Definitions

  • the present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.
  • Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material with a larger band gap than silicon (Si), and is applied to various semiconductor devices such as power elements, environmental elements, high-temperature operating elements, and high-frequency elements. Has been. Especially, application to power devices, such as a switching element and a rectifier, attracts attention.
  • MOSFET Metal-semiconductor field effect transistors
  • MOSFET Metal-oxide film-semiconductor field-effect transistor
  • These switching elements can be switched between an on state and an off state by controlling a voltage applied to a gate electrode which is a component of the switching element.
  • a drain current of several A (amperes) or more can flow. Further, no drain current flows in the off state, and a high breakdown voltage of several hundred volts or more can be realized.
  • SiC has a higher dielectric breakdown electric field and a higher thermal conductivity than Si, so it is easy to increase the breakdown voltage and reduce the loss. For this reason, in order to realize the same performance, the size (area, thickness, etc.) of the device can be greatly reduced with respect to the Si power device.
  • An SiC power device such as a vertical MOSFET typically has a structure in which a plurality of unit cells are arranged.
  • a general configuration of each unit cell is described in Patent Document 1, for example.
  • the electrode of each unit cell is connected to the wiring provided above the electrode.
  • the gate electrode of each unit cell is connected to the gate electrode upper metal wiring formed on the gate electrode
  • the source electrode of each unit cell is the source electrode upper metal formed on the source electrode.
  • the source and gate electrode upper metal interconnections are preferably formed using the same conductive film (for example, Patent Document 2).
  • an aluminum (Al) film is used as the conductive film.
  • the “upper metal wiring” here may be a wiring for connecting the electrodes of each unit cell, and extends from the electrode pads (wire bonding pads) such as source pads and gate pads. Also included is a wired connection.
  • Al diffuses from the upper metal wiring (Al wiring), which may cause a decrease in reliability and a decrease in element characteristics. Therefore, in order to suppress Al diffusion, it has been proposed to dispose a barrier metal layer as a base of the upper metal wiring.
  • Patent Document 3 discloses that in a Si power device (vertical MOSFET), a barrier metal layer and a conductive layer containing Al are stacked in this order and patterned to form a gate wiring. (FIG. 9 and 31st paragraph of Patent Document 3).
  • the chip area can be significantly reduced compared to Si power devices, but since the amount of current flowing through the device does not change, the density of current flowing through the upper metal wiring (source metal upper metal wiring in MOSFET) increases. . Therefore, in order to ensure the reliability of the upper metal wiring, it is necessary to increase the thickness of the upper metal wiring.
  • the thickness of the upper metal wiring is larger than the thickness of the upper metal wiring of the Si power device, and is set to 2 ⁇ m or more (for example, about 3 ⁇ m).
  • the wiring processing technology there are mainly wet etching technology and dry etching technology.
  • dry etching technique anisotropy and dimensional accuracy are high and reproducibility is excellent.
  • dry etching is often used for wiring processing of general semiconductor elements.
  • the dimensional accuracy decreases as the wiring becomes thicker.
  • the selection ratio with a photoresist film (hereinafter referred to as “resist film”) serving as an etching mask is lower than the selection ratio of wet etching, it is applied to the processing of wiring having a thickness exceeding about 2 ⁇ m. It ’s difficult.
  • wet etching is preferably used for processing the upper metal wiring of the SiC power device.
  • a barrier metal layer for example, a titanium (Ti) layer
  • Such a wiring structure is obtained, for example, by forming a laminated film including a Ti film serving as a barrier metal layer and an Al film serving as an upper metal wiring, and patterning the laminated film. Considering the thickness of the upper metal wiring, it is preferable to use wet etching for patterning the laminated film.
  • the etching rate of Al was remarkably higher than that in the case of wet etching of a single Al film. This is presumably because the local battery was formed by the difference in standard electrode potential between Al and the barrier metal (for example, Ti). In this specification, the phenomenon that the etching rate of the upper wiring metal is increased by the local battery is referred to as “local battery effect”.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to suppress deterioration of element characteristics due to diffusion of metal from an upper metal wiring in a semiconductor device using silicon carbide, while suppressing the upper metal.
  • the purpose is to increase the dimensional accuracy of the wiring and to ensure high yield and reliability.
  • the semiconductor device includes a substrate, a silicon carbide layer formed on the surface of the substrate, a first electrode and a second electrode formed on the silicon carbide layer and electrically insulated from each other, and the carbonization.
  • a second barrier metal layer connected to the second electrode is provided, and the first barrier metal is formed inside the outline of the first metal wiring as viewed from above the substrate.
  • An outline is arranged, and the outline of the second barrier metal is arranged inside the outline of the second metal wiring.
  • each part of the entire surface of the first barrier metal layer is covered with the first electrode, the first metal wiring or the insulating film, and each part of the entire surface of the second barrier metal layer. Is covered with the second metal, the second metal wiring or the insulating film.
  • the first barrier metal layer is formed in the first contact hole and on the insulating film, and an upper surface and a side wall of the first barrier metal layer are covered with the first metal wiring.
  • the second barrier metal layer is formed in the second contact hole and on the insulating film, and an upper surface and a side wall of the second barrier metal layer are covered with the second metal wiring.
  • the first and second metal wirings are preferably formed by patterning the same conductive film.
  • the first and second metal wirings are separated from each other by an isolation region located between the first and second metal wirings, and the first barrier metal layer and the second barrier metal None of the layers are exposed in the isolation region.
  • the first and second barrier metal layers are preferably formed by patterning the same metal film.
  • the thickness of the first and second metal wirings may be 2 ⁇ m or more.
  • the shortest distance Y1 between the contour of the first metal wiring and the contour of the first barrier metal is 1 ⁇ m or more, and the contour of the second metal wiring and the second barrier
  • the shortest distance Y2 from the metal outline may be 1 ⁇ m or more.
  • the first and second metal wirings may be aluminum layers.
  • the first and second barrier metal layers may include titanium.
  • the first and second barrier metal layers may be a laminated film including a titanium film and a titanium nitride film.
  • the first electrode may be a source electrode, and the second electrode may be a gate electrode.
  • the substrate is a first conductivity type silicon carbide substrate, a second conductivity type well region formed in the silicon carbide layer, formed in the well region, and the well region A contact region containing a second conductivity type impurity at a higher concentration, a first conductivity type source region formed in the well region so as to surround the contact region, and the silicon carbide layer, A first conductivity type drift region formed in a portion where none of the well region, the contact region, and the source region is formed, a gate insulating film formed on the silicon carbide layer, and a back surface of the substrate A drain electrode formed, and the source electrode is formed on the silicon carbide layer so as to be in contact with the contact region and the source region.
  • the gate electrode is formed on the gate insulating film.
  • the method of manufacturing a semiconductor device of the present invention includes (A) a step of forming a silicon carbide layer on a substrate, and (B) a first electrode and a second electrode that are electrically insulated from each other on the silicon carbide layer. And (C) forming an insulating film on the silicon carbide layer and the first and second electrodes, and forming a first contact hole reaching the first electrode and the second electrode on the insulating film Forming a second contact hole reaching; (D) forming a metal film in the first and second contact holes and on the insulating film; and (E) patterning the metal film, A first barrier metal layer connected to the first electrode in one contact hole and electrically separated from the first barrier metal layer and connected to the second electrode in the second contact hole Second Beauty Obtaining a metal layer; (F) forming a conductive film on the first barrier metal layer, the second barrier metal layer, and the insulating film; and (G) patterning the conductive film by wet etching.
  • first metal wiring connected to the first barrier metal layer and a second metal wiring electrically isolated from the first metal wiring and connected to the second barrier metal layer.
  • the contour of the first barrier metal is disposed inside the contour of the first metal wiring
  • the contour of the second barrier metal is disposed inside the contour of the second metal wiring. The contour is arranged.
  • the step (G) includes a step of etching the conductive film to form an isolation region for isolating the first metal wiring and the second metal wiring from each other. Neither the first barrier metal layer nor the second barrier metal layer is exposed in the isolation region.
  • the thickness of the conductive film may be 2 ⁇ m or more.
  • the conductive film may be an aluminum film.
  • the metal film may be a laminated film including a titanium film and a titanium nitride film.
  • the first electrode may be a source electrode, and the second electrode may be a gate electrode.
  • the barrier metal is disposed as the base of the upper metal wiring, it is possible to suppress deterioration of element characteristics due to diffusion of the metal contained in the upper metal wiring. Further, it is possible to prevent the dimensional accuracy of the upper metal wiring from being lowered due to the barrier metal while ensuring the thickness of the upper metal wiring. Therefore, the yield can be increased and the reliability can be improved.
  • the method for manufacturing a semiconductor device of the present invention when the upper metal wiring is formed by wet etching, the local battery effect caused by the exposure of the barrier metal can be suppressed. As a result, an increase in the etching rate of the upper metal wiring can be prevented, and the dimensional accuracy of the upper metal wiring with respect to the mask pattern on the resist film can be increased.
  • FIG. 1 is a schematic plan view of a vertical MISFET 100 according to a first embodiment of the present invention.
  • (A) to (c) are partial cross-sectional views taken along lines I-I ′, II-II ′, and III-III ′ in the MISFET shown in FIG. 1, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively.
  • (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the vertical MISFET of 1st Embodiment by this invention, respectively. It is a typical top view of other vertical type MISFET200 of a 1st embodiment by the present invention.
  • (A) to (c) are process cross-sectional views for explaining a reference example of a method of forming a wiring by wet etching, and a diagram for explaining a local battery effect generated when the wiring is formed. is there.
  • the present inventors have found that when wet etching is used for processing the upper metal wiring and the barrier metal layer, the local battery effect is produced, resulting in a decrease in dimensional accuracy of the upper metal wiring.
  • 8A to 8C are cross-sectional process diagrams illustrating a reference example of the process of forming the upper metal wiring and the barrier metal layer.
  • a Ti film 51 and an Al film 53 are formed in this order.
  • a mask layer 55 is disposed on the Al film 53.
  • the thickness of the Al film 53 is 2 ⁇ m or more, for example, 3 ⁇ m, and the thickness of the Ti film is, for example, 50 nm.
  • wet etching is performed on the Ti film 51 and the Al film 53 using the mask layer 55 as an etching mask.
  • etching solution for example, a mixed solution of phosphoric acid and nitric acid is used.
  • Al etching proceeds at a uniform speed, and the portion of the Al film not covered with the mask layer 55 is removed, and the surface of the Ti film 51 is removed. Is exposed. A portion 53 a of the Al film that remains without being etched has a shape defined by the mask layer 55.
  • an Al layer 54 serving as an upper metal wiring and a Ti layer 52 serving as a barrier metal layer are formed.
  • the pattern of the Al layer 54 and the Ti layer 52 is smaller than the pattern defined by the mask layer 55.
  • the distance dZ between the end of the Al layer 54 and the end of the mask layer 55 may be 5 ⁇ m or more, for example.
  • the width of the mask layer 55 is small, the entire Al layer 53a may be removed due to the local battery effect.
  • the case where the Al layer is used as the upper metal wiring and the Ti layer is used as the barrier metal layer has been described as an example.
  • the local battery effect is not only when these materials are used, but also the standard electrode potential of the metal of the upper metal wiring. It may occur when the standard electrode potential of the barrier metal is smaller than that.
  • the barrier metal layer is exposed even at one location, and when a local battery is generated, the Al metal is electrically connected to the exposed portion of the barrier metal layer. It was also found that the entire Al film might be affected by the local battery.
  • the reliability of the upper metal wiring cannot be ensured in a power silicon carbide element through which a large current flows.
  • the barrier metal layer is not provided, the local battery effect does not occur, but the metal (Al) of the upper metal wiring diffuses and there is a risk of deteriorating element characteristics.
  • Al of the upper metal wiring diffuses into the gate insulating film, it causes a leakage current.
  • Al diffuses into an electrode such as a source electrode the resistance of the electrode increases, so that the on-resistance may increase.
  • the present inventor examined a configuration for suppressing the local battery effect while securing the thickness of the upper metal wiring and preventing the diffusion of the metal from the upper metal wiring using the barrier metal. It came to.
  • the semiconductor device of this embodiment is a vertical MISFET using silicon carbide.
  • FIG. 1 is a plan view of a vertical MISFET 100 using silicon carbide according to the present embodiment.
  • FIGS. 2A to 2C are views taken along lines II ′ and II ⁇ in the plan view shown in FIG.
  • FIG. 3 is a partial cross-sectional view taken along line II ′ and line III-III ′.
  • the MISFET 100 includes a substrate 1 and a plurality of unit cells 30 supported by the substrate 1. These unit cells 30 are arranged two-dimensionally. On the upper part of the unit cell 30, a wiring 11A connected to the source electrode of each unit cell 30 and a wiring 12A connected to the gate electrode 9 of each unit cell 30 are provided. These wirings 11A and 12A are separated from each other by the separation region 32.
  • the wiring 11 ⁇ / b> A includes a source electrode upper metal wiring (also referred to as “first metal wiring”) 11 and a barrier metal layer (also referred to as “first barrier metal layer”) 16.
  • the barrier metal layer 16 is disposed between the source electrode upper metal wiring 11 and the source electrode. Further, when viewed from above the substrate 1, that is, in the plan view shown in FIG. 1, the contour of the barrier metal layer 16 is arranged inside the contour of the source electrode upper metal wiring 11.
  • the wiring 12 ⁇ / b> A includes a gate electrode upper metal wiring (also referred to as “second metal wiring”) 12 and a barrier metal layer (also referred to as “second barrier metal layer”) 17.
  • the barrier metal layer 17 is disposed between the gate electrode upper metal wiring 12 and the gate electrode 9. Further, when viewed from above the substrate 1, that is, in the plan view shown in FIG. 1, the contour of the barrier metal layer 17 is arranged inside the contour of the gate electrode upper metal wiring 12.
  • the upper metal wirings 11 and 12 and the isolation region 32 are preferably formed by patterning the same conductive film (for example, an Al film).
  • the isolation region 32 is a region formed by removing a part of the conductive film, and is defined by the side surface of the upper metal wiring 11 and the side surface of the upper metal wiring 12 facing this side surface.
  • the barrier metal layers 16 and 17 are preferably formed by patterning the same metal film (for example, a Ti film, a TiN film, or a laminated film of a Ti film and a TiN film).
  • the gate electrode 9 has a gate portion 9g functioning as a gate in each unit cell 30, and a gate connection portion 9c for connecting the wiring 12A and the gate portion 9g.
  • the configuration of the gate electrode 9 of the present embodiment is not limited to the illustrated configuration.
  • the gate portion 9 g may also be connected to the gate electrode upper metal wiring 12 through the barrier metal layer 17.
  • Each unit cell 30 includes a substrate 1, a silicon carbide layer 20 formed by epitaxial growth on the main surface of the substrate 1, and a gate electrode 9 provided on the silicon carbide layer 20 via a gate insulating film 6.
  • Source electrode 8 in contact with the surface of silicon carbide layer 20 and drain electrode 7 provided on the back surface of substrate 1.
  • SiC substrate a low-resistance n-type silicon carbide substrate
  • Silicon carbide layer 20 includes well region 3 having a conductivity type (p-type in this case) different from that of SiC substrate 1 and drift region 2 including a portion of silicon carbide layer 20 where well region 3 is not formed. And are formed.
  • Drift region 2 is an n ⁇ type silicon carbide layer containing n type impurities at a lower concentration than SiC substrate 1.
  • the well region 3 is disposed so as to be surrounded by the n-type source region 5 containing high-concentration n-type impurities and the source region 5, and contains p-type impurities at a higher concentration than the well region 3.
  • a p + -type contact region 4 is formed.
  • Well region 3, source region 5 and contact region 4 are formed by implanting impurity ions into silicon carbide layer 20.
  • the contact region 4 and the source region 5 are in ohmic contact with the source electrode 8, respectively. Therefore, the well region 3 is electrically connected to the source electrode 8 through the contact region 4.
  • the gate insulating film 6 and the gate electrode 9 are connected to the end of the source region 5 in the adjacent well region 3 across the drift region 2 between the well regions from the end of the source region 5 in one well region 3. Covers up to.
  • the silicon carbide layer 20, the source electrode 8 and the gate electrode 9 are covered with an interlayer insulating film 10.
  • a contact hole 13 reaching the source electrode 8 is provided in the interlayer insulating film 10.
  • a barrier metal layer 16 is formed in the contact hole 13 so as to be in contact with the source electrode 8.
  • the source electrode upper metal interconnection 11 is formed in the contact hole 13 and on the interlayer insulating film 10 so as to be in contact with the upper surface of the barrier metal layer 16. Accordingly, the source electrode 8 of each unit cell 30 is connected to the source electrode upper metal wiring 11 via the barrier metal layer 16.
  • the gate electrodes 9 of the unit cells 30 are connected to each other as can be seen from the plan view shown in FIG. Specifically, the gate electrode 9 in the present embodiment has an opening that opens the source region 5 and the contact region 4 of each unit cell 30, but is not separated between unit cells. The gate electrode 9 is also extended to below the gate electrode upper metal wiring 12 (gate connection portion 9c).
  • the interlayer insulating film 10 is provided with a contact hole 15 reaching the gate electrode 9 (here, the gate connection portion 9c).
  • a barrier metal layer 17 is formed in the contact hole 15 so as to be in contact with the gate connection portion 9c.
  • Gate electrode upper metal interconnection 12 is formed in contact hole 15 and on interlayer insulating film 10 so as to be in contact with the upper surface of barrier metal layer 17. In this way, the gate electrode 9 is connected to the gate electrode upper metal wiring 12 through the barrier metal layer 17.
  • the side surface and the upper surface of the barrier metal layer 16 are covered with the source electrode upper metal wiring 11.
  • the side and upper surfaces of the barrier metal layer 17 are covered with the gate electrode upper metal wiring 12.
  • the barrier metal layer 16 is not provided on the side surface 11As of the wiring 11A
  • the barrier metal layer 17 is not provided on the side surface 12As of the wiring 12A.
  • FIG. 2B shows the cross-sectional structure of the portion of the peripheral portion of the wiring 11A on the separation region 32 side, the cross section of the other portion of the peripheral portion of the wiring 11A (along the line III-III ′).
  • the cross section also has a structure similar to that shown in FIG. That is, as shown in FIG. 2C, the side surface and the upper surface of the barrier metal layer 16 are covered with the source electrode upper metal wiring 11, and the barrier metal layer 16 is not provided on the side surface 11As of the wiring 11A.
  • the barrier metal layers 16 and 17 do not exist on the entire lower surface of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12, but a part of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12. A part of is in direct contact with the interlayer insulating film 10.
  • a film (Ti film) 51 including a barrier metal and a conductive film (Al film) 53 for forming an upper metal wiring are deposited, and these films are simultaneously wetted.
  • a barrier metal layer (Ti layer) 52 and an upper metal wiring (Al layer) 54 are formed.
  • the barrier metal layer 52 and the upper metal wiring 54 have substantially the same planar shape. Therefore, the barrier metal layer 52 exists on the entire lower surface of the upper metal wiring 54. Further, when viewed from above the substrate, the contour of the upper metal wiring 54 and the contour of the barrier metal layer 52 substantially coincide.
  • a wiring for example, an electrode pad
  • the contours of the barrier metal layers 16 and 17 are arranged inside the contours of the upper metal wirings 11 and 12, respectively, as viewed from above the substrate 1. Further, the barrier metal layers 16 and 17 are not provided on the side surfaces of the wirings 11A and 12A.
  • Such a configuration is realized by separately performing patterning for forming the barrier metal layers 16 and 17 and patterning for forming the upper metal wirings 11 and 12. For example, after the barrier metal layers 16 and 17 are formed, a conductive film that covers the barrier metal layers 16 and 17 is formed. Next, only the conductive film is etched to obtain the upper metal wirings 11 and 12. A specific manufacturing process will be described in detail later.
  • each part of the entire surface of the barrier metal layer 16 is covered with the source electrode 8, the interlayer insulating film 10, or the source electrode upper metal wiring 11.
  • each part of the entire surface of the barrier metal layer 17 is covered with the gate electrode 9, the interlayer insulating film 10, or the gate electrode upper metal wiring 12.
  • the entire surface of the barrier metal includes all of the upper surface, the lower surface and the side surface of the barrier metal.
  • the interlayer insulating film 10 refers to an insulating film in which the contact holes 13 and 15 are formed, and does not include, for example, a passivation film deposited after the formation of the upper metal wiring. Note that the configuration of the present embodiment is not limited to the above configuration. If the surfaces of the barrier metal layers 16 and 17 are not exposed immediately after the etching of the conductive film, the effect of the present invention can be obtained. For example, another layer may be interposed between the barrier metal layers 16 and 17 and the interlayer insulating film 10.
  • the shape of the barrier metal layers 16 and 17 is not limited to the shape illustrated.
  • the barrier metal layer 16 only needs to be in contact with the source electrode 8 at least in the contact hole 13, and may be disposed only inside the contact hole 13.
  • the barrier metal layer 17 only needs to be in contact with the gate electrode 9 at least in the contact hole 15, and may be disposed only inside the contact hole 15.
  • FIG. 1 shows that the barrier metal layer 16 and 17 only needs to be in contact with the source electrode 8 at least in the contact hole 13, and may be disposed only inside the contact hole 13.
  • the metal of the upper metal wirings 11 and 12 (here In this case, Al) can be more effectively prevented from diffusing into the gate insulating film 6 and the source electrode 8 from the side walls of the contact holes 13 and 15 and the upper surface of the interlayer insulating film 10.
  • the shortest distance Y1 between the side surface 11As of the wiring 11A (that is, the side surface of the source electrode upper metal wiring 11) and the side surface of the barrier metal layer 16 is Preferably it is set to 1 ⁇ m or more, more preferably 2 ⁇ m or more.
  • the barrier metal layer 16 is exposed on the side surface of the wiring 11A even when patterning of the metal film including the barrier metal and mask misalignment in patterning of the conductive film for forming the upper metal wiring are taken into consideration. This can be prevented more reliably.
  • the shortest distance Y2 between the side surface 12As of the wiring 12A (that is, the side surface of the gate electrode upper metal wiring 12) and the side surface of the barrier metal layer 17 is preferably set to 1 ⁇ m or more, more preferably 2 ⁇ m or more.
  • these distances Y1 and Y2 are 3 ⁇ m or less.
  • the shortest distance X1 between the end face of the barrier metal layer 16 and the end portion of the contact hole 13 and the shortest distance X2 between the end face of the barrier metal layer 17 and the contact hole 15 are as follows when forming the contact holes 13 and 15, respectively. In consideration of misalignment of the mask, it is preferably 0.5 ⁇ m or more. On the other hand, in order to suppress an increase in the chip area, the distances X1 and X2 may be 2.0 ⁇ m or less. In order to more reliably suppress Al diffusion, the distance X1 may be longer than 2.0 ⁇ m. For example, the entire unit cell (the entire well region 3) located at the peripheral edge of the source electrode upper metal wiring 11 ) May be set to cover.
  • the distances Y1, Y2, X1, and X2 are all distances in a plane parallel to the surface of the substrate 1.
  • the distance Y1 is the distance between the contour of the source electrode upper metal wiring 11 and the contour of the barrier metal layer 16
  • the distance Y2 is the contour of the gate electrode upper metal wiring 12 and the barrier. It is the distance from the contour of the metal layer 17.
  • the barrier metal layers 16 and 17 can be easily deposited inside the contact holes 13 and 15 and have an adhesiveness to the upper metal wiring (Al wiring) formed on the barrier metal layers 16 and 17.
  • Al wiring upper metal wiring
  • the thickness of the barrier metal layers 16 and 17 is, for example, not less than 50 nm and not more than 100 nm.
  • the chip area can be significantly reduced as compared with the Si power device, but the current density is relatively high.
  • the thicknesses of the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12 are, for example, 2 ⁇ m or more so that the current density flowing through these wirings does not increase. More preferably, it is 3 ⁇ m or more.
  • 3 to 6 are process cross-sectional views for explaining the manufacturing process of the MISFET of this embodiment, and correspond to a cross section taken along line II-II 'shown in the plan view of FIG.
  • silicon carbide layer 20 is formed by epitaxially growing silicon carbide on the main surface of substrate 1.
  • a silicon carbide substrate is used as the substrate 1.
  • a 4H—SiC substrate having an off angle of 8 degrees from the (0001) Si plane toward the ⁇ 11-20> direction is used.
  • the conductivity type of the substrate 1 is n-type, and its impurity concentration is, for example, 1 ⁇ 10 18 cm ⁇ 3 or more and 5 ⁇ 10 19 cm ⁇ 3 or less.
  • the silicon carbide layer 20 is formed by thermal CVD using, for example, silane (SiH 4 ) and propane (C 3 H 8 ) as source gases, hydrogen (H 2 ) as a carrier gas, and nitrogen (N 2 ) gas as a dopant gas. Can be formed.
  • n-type silicon carbide layer 20 having an impurity concentration lower than that of silicon carbide substrate 1 is formed by epitaxial growth.
  • the impurity concentration and thickness of the silicon carbide layer 20 vary depending on specifications required for the MISFET. For example, when an MISFET having a withstand voltage of 600 V is to be manufactured, the impurity concentration of the silicon carbide layer 20 is 1 ⁇ 10 15 cm ⁇ 3 or more. It is desirable that it is 5 ⁇ 10 16 cm ⁇ 3 or less and the thickness is 5 ⁇ m or more.
  • impurity ions are implanted into the silicon carbide layer 20 to form the p-type well region 3, the p-type contact region 4, and the n-type source region 5.
  • these regions 3, 4, and 5 are formed as follows, for example. First, after a silicon oxide film is deposited on the silicon carbide layer 20 by a CVD method, the silicon oxide film is patterned by photolithography and dry etching to obtain an implantation mask for forming a well region.
  • p-type impurity ions for example, aluminum ions, boron ions, etc.
  • p-type impurity ions for example, aluminum ions, boron ions, etc.
  • An injection layer is formed.
  • the substrate temperature at the time of ion implantation is preferably set to, for example, 500 ° C. or higher in order to reduce defects due to implantation.
  • the implantation mask is removed using hydrofluoric acid.
  • an implantation layer that becomes the p-type contact region 4 is formed by implanting p-type impurity ions into the silicon carbide layer 20.
  • an implantation layer to be the source region 5 is formed by implanting n-type impurity ions (for example, nitrogen ions, phosphorus ions, etc.) into the silicon carbide layer 20.
  • n-type impurity ions for example, nitrogen ions, phosphorus ions, etc.
  • an activation annealing for 30 minutes is performed on these implantation layers at a temperature of about 1700 ° C. in an inert atmosphere such as argon, thereby obtaining a well region 3, a contact region 4 and a source region 5, respectively.
  • the impurity concentration of the well region 3 obtained by the above method is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less, and the depth of the well region 3 is, for example, 0 to prevent pinch-off. .About 5 ⁇ m.
  • the impurity concentration of the contact region 4 is higher than the impurity concentration of the well region 3 and is, for example, 1 ⁇ 10 18 cm ⁇ 3 or more. If the impurity concentration of the contact region 4 is higher than the impurity concentration of the well region 3, it is easy to form an ohmic junction between the contact region 4 and a source electrode to be formed later.
  • the depth of the contact region 4 (depth from the surface of the silicon carbide layer 20) is, for example, about 300 nm.
  • the impurity concentration of the source region 5 is at least 1 ⁇ 10 19 cm ⁇ 3 or more, preferably 6 ⁇ 10 19 cm ⁇ 3 or more, more preferably 1 ⁇ 10 20 cm ⁇ 3 .
  • the depth of the source region 5 is about 300 nm, for example.
  • the gate insulating film 6, the source electrode 8, and the gate electrode 9 are formed on the surface (main surface) of the silicon carbide layer 20, and the drain electrode 7 is formed on the back surface.
  • interlayer insulating film 10 is formed so as to cover gate insulating film 6, gate electrode 9, source electrode 8, and silicon carbide layer 20 exposed on the main surface side.
  • the gate insulating film 6 can be formed, for example, by thermally oxidizing the surface of the silicon carbide layer 20. Specifically, the wafer-like silicon carbide substrate 1 is held in a quartz tube, and bubbled oxygen is introduced at a flow rate of 2.5 SLM (l / s) while the quartz tube is kept at a temperature of 1100 ° C. The surface of silicon carbide layer 20 is thermally oxidized. The time for performing the thermal oxidation is, for example, 3 hours. Thereby, a silicon oxide film (thermal oxide film) having a thickness of about 40 nm is obtained as the gate insulating film 6 on the surface of the silicon carbide layer 20.
  • the gate electrode 9 is preferably formed using polycrystalline silicon having excellent heat resistance and conductivity. This is because the melting point of polycrystalline silicon is 1420 ° C., which is sufficiently higher than the temperature of heat treatment (for example, 1000 ° C.) at the time of forming a source electrode performed in a later step.
  • a polycrystalline silicon film (not shown) is deposited on the gate insulating film 6 by using a low pressure CVD method. Specifically, by using silane and phosphine as source gases, maintaining the pressure at 95 Pa and the growth temperature at 550 ° C. for 8 hours, the n-type impurity concentration is 7 ⁇ 10 20 cm ⁇ 3 and the thickness is 500 nm. A crystalline silicon film is obtained. The polycrystalline silicon film is patterned by photolithography and dry etching to obtain the gate electrode 9.
  • Gate electrode 9 is a portion of the surface of well region 3 where a channel is formed, that is, source region 5 and drift region 2 (a region composed of a portion of silicon carbide layer 20 where well region 3 is not formed). It suffices to cover at least the portion 34 located between them, and the pattern is not particularly limited.
  • the source electrode 8 is formed, for example, by depositing nickel on the entire surface or a part of the p-type contact region 4 and the n-type source region 5.
  • Nickel (not shown) is deposited to a thickness of 100 nm on the entire surface including the p-type contact region 4 and the n-type source region 5 by sputtering.
  • the source electrode 8 is formed by performing patterning by photolithography and etching on the nickel and leaving nickel only on the entire surface or part of the p-type contact region 4 and the n-type source region 5.
  • the source electrode 8 needs to cover a part of each of the p-type contact region 4 and the n-type source region 5, but the pattern is not particularly limited, and the p-type contact region 4 and the n-type contact region 4 There is no problem even if the entire surface of the source region 5 is covered.
  • a silicon oxide film having a high dielectric breakdown voltage and capable of being easily formed is formed as the interlayer insulating film 10.
  • the silicon oxide film can be formed using, for example, an atmospheric pressure CVD method, and the thickness thereof is, for example, 1 ⁇ m.
  • the drain electrode 7 is formed, for example, by depositing titanium on the back side of the silicon carbide substrate 1 and then performing heat treatment to form titanium silicide.
  • a contact hole 13 reaching the source electrode 8 and a contact hole 15 reaching the gate electrode 9 are formed in the interlayer insulating film 10.
  • These contact holes 13 and 15 can be formed using known photolithography and dry etching. As dry etching, for example, reactive ion etching (RIE) using CHF 3 or CF 4 may be performed.
  • RIE reactive ion etching
  • a metal film 22 including a barrier metal is formed on the entire surface of the interlayer insulating film 10 and the contact holes 13 and 15.
  • a stacked film containing titanium (Ti) and titanium nitride (TiN) is formed as the metal film 22.
  • titanium (Ti) and titanium nitride (TiN) are deposited in this order by a reactive sputtering method to obtain a metal film 22 having a total thickness of about 50 nm.
  • a photoresist is applied on the metal film 22, and a part of the photoresist is exposed and patterned. As a result, a resist layer 24 covering the contact hole 13 and its peripheral portion and a resist layer 25 covering the contact hole 15 and its peripheral portion are obtained.
  • the metal film 22 is processed by dry etching or wet etching.
  • wet etching a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the etching time is set to about 10 minutes. After the metal film 22 is etched, the resist layers 24 and 25 are removed.
  • the barrier metal layer 16 and the barrier metal layer 17 separated from each other are obtained from the metal film 22.
  • the barrier metal layer 16 is in contact with the source electrode 8 in the contact hole 13, and the barrier metal layer 17 is in contact with the gate electrode 9 in the contact hole 15.
  • the barrier metal layer 16 is formed so as to cover at least a portion of the side wall of the contact hole 13 and the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 13.
  • the barrier metal layer 17 is formed so as to cover at least a portion of the side wall of the contact hole 15 and the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 15.
  • Portions of the interlayer insulating film 10 that are not covered with the barrier metal layers 16 and 17 are exposed.
  • the upper surfaces 16u and 17u and the side surfaces (etched surfaces) 16s and 17s of the barrier metal layers 16 and 17 are exposed at this time.
  • an aluminum (Al) film is deposited on the barrier metal layers 16 and 17 and the interlayer insulating film 10 by vapor deposition or sputtering.
  • the thickness of the Al film is, for example, about 3 ⁇ m.
  • the Al film is patterned using known photolithography and wet etching to form the source electrode upper metal wiring 11 and the gate electrode upper metal wiring 12.
  • a mixed solution of phosphoric acid, nitric acid and acetic acid is used for the wet etching of the Al film. In this way, a wiring 11A including the source electrode upper metal wiring 11 and the barrier metal layer 16 and a wiring 12A including the gate electrode upper metal wiring 12 and the barrier metal layer 17 are obtained.
  • the source electrode upper metal wiring 11 obtained by wet etching is formed so as to cover the entire upper surface 16 u and side surface 16 s of the barrier metal layer 16.
  • the gate electrode upper metal wiring 12 is formed so as to cover the entire upper surface 17 u and side surface 17 s of the barrier metal layer 17. Therefore, the barrier metal layers 16 and 17 are not exposed on the side surfaces 11As and 12As of the wirings 11A and 12A. Thereafter, if necessary, a passivation film may be provided so as to cover the wirings 11A and 12A. In this way, the MISFET 100 is manufactured.
  • the barrier metal layer 16 includes the source electrode 8 in the contact hole 13 and the source electrode upper metal wiring 11, the side wall of the contact hole 13 (side wall of the interlayer insulating film 10), and the source electrode. It is formed only between the upper metal wiring 11 and between the source electrode upper metal wiring 11 and the portion of the upper surface of the interlayer insulating film 10 located near the upper end of the contact hole 13.
  • the barrier metal layer 17 is formed between the gate electrode 9 in the contact hole 15 and the gate electrode upper metal wiring 12, and between the side wall of the contact hole 15 (side wall of the interlayer insulating film 10) and the gate electrode upper metal wiring 12.
  • the barrier metal layer 16 may be provided at least between the source electrode 8 and the source electrode upper metal wiring 11 and not disposed on the side surface of the wiring 11A.
  • the barrier metal layer 17 may be provided at least between the gate electrode 9 and the gate electrode upper metal wiring 12 and not disposed on the side surface of the wiring 12A.
  • etching (wet etching) of the Al film for forming the upper metal wirings 11 and 12 is performed separately from the etching of the Ti / TiN film for forming the barrier metal layers 16 and 17.
  • Ti since Ti is not exposed on the etching surface, Ti does not contact the etching solution. Therefore, the local battery effect due to the difference in the standard electrode potential between Al and Ti does not occur, the increase in Al etching rate can be suppressed, and the variation in local etching rate can also be suppressed. In addition to ensuring, the processed shape can be further stabilized.
  • the shape of the upper wiring metals 11 and 12 in the present embodiment is not limited to the shape shown in FIG.
  • the gate electrode upper metal wiring 12 may be arranged at the center of the region where the plurality of unit cells are arranged.
  • the source electrode upper metal wiring 11 may have two source pads, and a gate wiring extended from the gate pad may be arranged in a gap between these pads.
  • FIG. 7 is a plan view showing another MISFET 200 of the present embodiment.
  • the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.
  • the source electrode upper metal wiring 11 has two source pads.
  • the gate electrode upper metal wiring 12 includes two gate pads 12p and a gate wiring 12a extending from the gate pads 12p.
  • the two gate pads 12p are connected by a gate wiring 12a.
  • the gate wiring 12 a is also disposed in the gap between the two source pads as viewed from above the substrate 1.
  • the connection portion between the gate electrode upper metal wiring 12 and the gate electrode can be provided not only on the gate pad 12p but also on the gate wiring 12a. Accordingly, it is possible to greatly reduce the wiring delay of the unit cells located at positions away from the gate pad 12p among the plurality of unit cells 30. As a result, the operation speed of the MISFET 200 can be further increased.
  • barrier metal layers 16 and 17 are provided under the upper metal wirings 11 and 12, respectively. Further, when viewed from above the substrate 1, the contours of the barrier metal layers 16 and 17 are arranged inside the contours of the upper metal wirings 11 and 12, respectively. Accordingly, the cross sections taken along lines IIa-IIa ′, IIb-IIb ′, and IIc-IIc ′ shown in FIG. 7 are all the same as the cross section shown in FIG. With such a configuration, as in the MISFET 100 shown in FIG. 1, the local battery effect can be suppressed, so that the dimensional accuracy of the upper metal wirings 11 and 12 can be improved.
  • the configuration of the unit cell 30 and the material of each component in the MISFET of the present embodiment are not limited to the configurations and materials described above with reference to FIGS.
  • a laminated film including a Ti film and a TiN film is used as the barrier metal layers 16 and 17.
  • the barrier metal layers 16 and 17 diffuse metal contained in the upper metal wirings 11 and 12. It is only necessary to include a metal having a function of suppressing the above, and the present invention is not limited to the above laminated film.
  • the barrier metal layers 16 and 17 may be a film containing, for example, Ti, TiN, tungsten, tungsten nitride, tantalum, or tantalum nitride, or may be a laminated film including two or more of these films.
  • the upper metal wirings 11 and 12 are preferably Al films.
  • the source electrode 8 and the gate electrode 9 do not have a silicide layer. However, even if both or one of these electrodes has a silicide layer, the same effect as described above can be obtained. it can. Similarly, although the drain electrode 7 in the above embodiment has a silicide layer, it may not have a silicide layer.
  • the source electrode 8 including the silicide layer is formed as follows, for example. First, a metal film (for example, Ni (nickel) film) is formed so as to be in contact with the silicon carbide layer 20. Next, annealing is performed (for example, in a nitrogen atmosphere at a temperature of 950 ° C. for about 1 minute) to react the silicon carbide layer 20 and the Ni film. Thereby, a part of Ni diffuses into the silicon carbide layer 20 and is alloyed to form a Ni silicide layer.
  • a metal film for example, Ni (nickel) film
  • a Ni silicide layer As the source electrode 8 and the drain electrode 7 because good ohmic contact with the silicon carbide layer 20 can be formed.
  • a Ti film or a cobalt (Co) film may be used as the metal film.
  • a Ti film When a Ti film is used, a Ti silicide layer is formed.
  • the Ti silicide layer does not have a function of barriering Al diffusion and is different from the “barrier metal layer” in this specification.
  • the “barrier metal layer” referred to in this specification is a metal film disposed between an electrode (for example, an electrode including a silicide layer) and an upper metal wiring, and is formed separately from the electrode.
  • the Ti silicide layer when a Ti silicide layer is formed as a source electrode, the Ti silicide layer needs to be separated for each unit cell. On the other hand, it is preferable that the barrier metal layer is not separated for each unit cell. Thereby, the spreading
  • MISFET 100 has an inverted channel structure, but may have a storage channel structure.
  • an oxide film is used as the gate insulating film 6, but an oxynitride film or a nitride film may be used.
  • a stacked film including two or more of an oxide film, an oxynitride film, and a nitride film may be used.
  • a high p + -type contact region 4 of the carrier concentration is provided than the well region 3, p + contact region 4 It may not be formed.
  • the carrier concentration of the well region 3 is sufficiently high, the high concentration p + contact region 4 may not be formed.
  • the conductivity type of silicon carbide substrate 1, silicon carbide layer 20, and source region 5 is n-type, and the conductivity type of well region 3 and contact region 4 is p-type. It is not limited.
  • the conductivity types of silicon carbide substrate 1, silicon carbide layer 20, and source region 5 may be p-type, and the conductivity types of well region 3 and contact region 4 may be n-type.
  • the 4H—SiC substrate is used as the substrate 1, other crystal planes or other polytype SiC substrates may be used.
  • the silicon carbide layer 20 may be formed on the Si surface
  • the drain electrode 7 may be formed on the C surface
  • the silicon carbide layer 20 may be formed on the C surface
  • the drain electrode 7 may be formed on the Si surface. May be.
  • the present invention is not limited to the vertical MISFET, but can be applied to other semiconductor devices using silicon carbide. More specifically, the present invention can be applied to various semiconductor devices having a silicon carbide layer, a plurality of electrodes provided on the silicon carbide layer, and upper metal wirings respectively connected to these electrodes.
  • the substrate 1 may be applied to a semiconductor device having a substrate other than a silicon carbide substrate.
  • the present invention is particularly advantageous when applied to a semiconductor device having a gate insulating film. As a result, an increase in leakage current due to diffusion of the metal of the upper metal wiring into the gate insulating film can be suppressed, so that deterioration in element characteristics can be more effectively suppressed.
  • the present invention can also be applied to a lateral MISFET.
  • the drain electrode is also formed on the silicon carbide layer.
  • the drain electrode is not provided on the back surface of the substrate 1, and one of the source electrodes 8 provided in each adjacent unit cell may be used as the source electrode and the other as the drain electrode.
  • the present invention is applied to a lateral MISFET, at least two of the wirings connected to the source electrode, the drain electrode, and the gate electrode each have a barrier metal layer and an upper metal wiring, and the barrier is viewed from above the substrate. If the contour of the metal layer has a structure arranged inside the contour of the upper metal wiring, the effect of the present invention can be obtained.
  • At least a wiring connected to the gate electrode has the above structure.
  • the metal (such as Al) contained in the upper metal wiring can be prevented from diffusing into the gate insulating film, so that the reliability of the semiconductor device can be improved more effectively.
  • each of the wirings connected to the source electrode, the drain electrode, and the gate electrode has the above structure.
  • the MISFET is manufactured using the SiC substrate 1 having the same conductivity type as that of the silicon carbide layer 20, but the insulated gate bipolar transistor (Insulated) using a SiC substrate having a conductivity type different from that of the silicon carbide layer 20.
  • Gate Bipolar Transistor (IGBT) can also be manufactured.
  • the present invention can also be applied to MESFETs.
  • the present invention it is possible to stabilize the wet etch rate when forming the wiring while securing the thickness of the wiring and to increase the dimensional accuracy with respect to the mask pattern on the resist.
  • the yield of semiconductor devices using silicon carbide can be increased and the reliability can be improved.
  • the present invention can be widely applied to semiconductor devices using silicon carbide, such as vertical MISFETs, horizontal MISFETs, IGBTs, and the like.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs (100) comportant, une couche de carbure de silicium, des première et deuxième électrodes formées sur la couche de carbure de silicium, un film isolant formé sur la couche de carbure de silicium et les première et deuxième électrodes et dans lequel sont formées des première et deuxième fenêtres de contact s'étendant respectivement jusqu'aux première et deuxième électrodes, des premier (11) et deuxième (12) câblages métalliques formés sur le film isolant et mutuellement isolés électriquement, une première couche barrière métallique (16) formée entre le premier câblage métallique (11) et la première électrode et en contact avec le premier câblage métallique (11), connecté, dans la première fenêtre de contact, à la première électrode, et une deuxième couche barrière métallique (17) formée entre le deuxième câblage métallique (12) et la deuxième électrode et en contact avec le deuxième câblage métallique (12), connecté, dans la deuxième fenêtre de contact, à la deuxième électrode. Vue du sommet du support (1), le bord de la première couche barrière métallique (16) est situé à l'intérieur du contour du premier câblage métallique (11) et le bord de la deuxième couche barrière métallique (17) est situé à l'intérieur du contour du deuxième câblage métallique (12).
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CN106549045A (zh) * 2015-09-17 2017-03-29 富士电机株式会社 半导体装置及半导体装置的制造方法
JP2017059720A (ja) * 2015-09-17 2017-03-23 富士電機株式会社 半導体装置および半導体装置の製造方法
US11456359B2 (en) 2015-09-17 2022-09-27 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
JP2022050236A (ja) * 2020-09-17 2022-03-30 富士電機株式会社 半導体装置および半導体装置の製造方法
JP7647042B2 (ja) 2020-09-17 2025-03-18 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2025068087A1 (fr) * 2023-09-29 2025-04-03 Infineon Technologies Austria Ag Procédé de formation d'électrodes et dispositif à semi-conducteur
WO2025197966A1 (fr) * 2024-03-21 2025-09-25 株式会社Power Diamond Systems Dispositif à semi-conducteur en diamant et procédé de fabrication de dispositif à semi-conducteur en diamant

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