WO2012000708A1 - Circuit pour une entrée numérique - Google Patents

Circuit pour une entrée numérique Download PDF

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Publication number
WO2012000708A1
WO2012000708A1 PCT/EP2011/057512 EP2011057512W WO2012000708A1 WO 2012000708 A1 WO2012000708 A1 WO 2012000708A1 EP 2011057512 W EP2011057512 W EP 2011057512W WO 2012000708 A1 WO2012000708 A1 WO 2012000708A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit arrangement
arrangement according
field effect
effect transistor
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2011/057512
Other languages
German (de)
English (en)
Inventor
Harald Karl
Rainer Viertler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of WO2012000708A1 publication Critical patent/WO2012000708A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • H03K17/795—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar transistors
    • H03K17/7955—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar transistors using phototransistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching

Definitions

  • Circuit arrangement for a digital input The invention relates to a circuit arrangement for a digital input of an electronic device.
  • Digital inputs in automation devices in industry or power engineering are operated with different nominal voltages and alternating and direct voltages, which are typically in the range between 24 V DC and 230 V AC. They are also often subject to high demands on their electromagnetic compatibility and their relevant immunity to interference.
  • US 4,275,307 A discloses an input circuit for a digital system having a rectifier, a dynamic current limiting circuit, a plurality of Zener diodes, and a light emitting element.
  • US Pat. Nos. 5,672,919 and DE 10 2007 025 243 B3 disclose digital input circuits which each contain a rectifier, a separating element for the galvanic isolation of the input circuit, a blocking element for the voltage-dependent blocking of the current flow and a self-conducting field-effect transistor for limiting the current.
  • Further input circuits with optocouplers for their galvanic isolation are known from US 5 539 352 A, JP 7-46111 A, JP 2-135819 A, US 4 197 471 A and GB 1 403 110 A. It is an object of the invention to provide an improved formwork ⁇ processing arrangement for a digital input of an electronic device, which is particularly suitable for a wide input voltage range.
  • the inventive circuit arrangement for a digital ⁇ input of an electronic device comprises at least one rectifier for rectifying a current flow through the circuit arrangement, a downstream rectifier self-conducting field-effect transistor is a downstream of the self-conducting field-effect transistor blocking member for blocking the current flow below a switching threshold of a one ⁇ output voltage, and the Blocking member downstream isolator for galvanic isolation of the digital input of we ⁇ least one coupled to him another component of the electronic device.
  • the most essential component of the circuit arrangement according to the invention is the self-conducting field effect transistor.
  • Such transistors can be obtained with very high blocking voltages and thus enable a regulation of the current flow through the circuit arrangement in a wide input voltage range, which can cover in particular the entire range between 24 V DC and 230 V AC. This advantageously enables the construction of a digital input for such a wide input voltage range, for otherwise various conventional digital inputs for each ⁇ parts of this
  • the other components of the circuit advantageously allow rectification of the current flow through the Circuitry for their protection against harmful input voltages wrong polarity and as polarity reversal in DC operation of the circuit, the realization of a switching threshold of the circuit as a function of the input signal strength, and the galvanic isolation of the digital input coupled with him further compo ⁇ len of the electronic device.
  • the rectifier is preferably a semiconductor diode or a bridge rectifier.
  • a bridge rectifier by its full-wave rectification of the electric current allows a faster response of the digital input to AC input voltages than the semiconductor diode, and is therefore preferably for appli ⁇ tions provided in which such a rapid response is advantageous.
  • the use of a semi-conductor diode ⁇ is preferred as the rectifier, since it is less expensive realized sierbar over the use of a bridge rectifier and reduces the total power loss of the digital input.
  • the bridge rectifier causes a current flow both at a positive and a negative input voltage and thus at an applied AC input voltage for both half-waves of the input voltage.
  • the self-conducting field-effect transistor is a depletion metal oxide semiconductor field effect transistor ⁇ .
  • a depletion metal oxide semiconductor field effect transistor ⁇ Preferably have a control terminal and a source terminal of the self-conducting metal oxide semiconductor Feldef ⁇ Anlagentransistors a current control resistance verbun ⁇ .
  • the current control resistor ensures when current flows for a voltage at the control terminal of the field effect transistor, which adjusts the current according to the characteristic of the Feldef ⁇ Stammtransistors.
  • the field effect transistor acts as a dynamic current source of the Wegungsanord ⁇ tion.
  • the self-conducting field effect transistor is a self-conducting junction field effect transistor.
  • the blocking member is preferably removable ⁇ det as a Zener diode.
  • the isolator is preferably designed as an optocoupler.
  • An embodiment of the circuit arrangement according to the invention provides at least one protective element for protection against input interference voltages. As a result, requirements for immunity to interference of the digital input can advantageously be met.
  • a protective element is preferably a suppressor diode or a varistor for protecting against input voltages exceeding a protection threshold.
  • the circuit arrangement and especially the field effect transistor contained in it can be protected against harmful overvoltages. This is particularly advantageous because field effect transistors can easily be destroyed by overvoltages.
  • the circuit arrangement can have at least one interference suppression capacitor as a protective element against input voltages whose frequency exceeds a protective frequency.
  • the circuit arrangement can be advantageously protected against harmful high-frequency voltages.
  • a further embodiment of the circuit arrangement provides for a first bypass capacitor electrically connected in parallel with the current control resistor .
  • This embodiment is particularly advantageous if the circuit arrangement is preceded by a relay.
  • the relay contacts may be oxidized, thereby affecting the reliability of the overall circuit consisting of the relay and the circuitry.
  • Through the first bypass capacitor of Stromsteue- is briefly approximately resistance at least partially bypassed, thereby setting a higher current flow, which advantageously allows for Rei ⁇ n Trent of the relay contacts after the switching of the relay.
  • Another embodiment of the circuit arrangement provides for the current control resistor electrically maral ⁇ ended bypass optocoupler before.
  • a further embodiment of the circuit arrangement provides a second bypass capacitor electrically connected in parallel with the isolator and / or a third bypass capacitor.
  • the third bypass capacitor is electrically parallel to a self-conducting Field effect transistor, the blocking member and the separator ent ⁇ held part of the circuit connected.
  • FIG. 1 shows a first circuit arrangement for a digital input of an electronic device according to the prior art
  • FIG 2 shows a second circuit arrangement for a digital input of an electronic device according to the prior art
  • FIG 3 shows a first embodiment of a erfindungsge ⁇ MAESSEN circuit arrangement for a digital input of an electronic device
  • FIG. 4 shows a second embodiment of a erfindungsge ⁇ MAESSEN circuit arrangement for a digital input of an electronic device
  • FIG. 5 shows a third embodiment of a erfindungsge ⁇ MAESSEN circuit arrangement for a digital input of an electronic device
  • FIG. 6 shows a fourth exemplary embodiment of a circuit arrangement according to the invention for a digital input of an electronic device
  • FIG. 7 shows a fifth embodiment of a erfindungsge ⁇ MAESSEN circuit arrangement for a digital input of an electronic device
  • FIG. 8 shows a sixth embodiment of a fiction, ⁇ contemporary circuit arrangement for a digital input of an electronic device. Corresponding parts are provided in all figures with the same reference numerals.
  • FIG. 1 shows a first conventional circuit arrangement for a digital input of an electronic device, for example an automation device used in industry or energy technology.
  • the circuit arrangement comprises a semiconductor diode D, a of the semiconductor diode D downstream Zener diode V z, a Zener diode Vz downstream resistor R v and a series resistor R v downstream optocoupler 0 T with a light emitting diode L as an optical transmitter and a photo-transistor PT as an optical Receiver.
  • the semiconductor diode D is used to rectify a current flow through the circuit arrangement, the zener diode V z de ⁇ defines a switching threshold of the digital input, the Vorwi ⁇ resistance R v limits the electrical current flow through the light emitting diode L of the optocoupler 0 T , and the optocoupler 0 T.
  • Such a circuit arrangement has the disadvantage that it can be used only for a relatively small range of input voltages U applied to the digital input. Namely, by the series resistor R v , the current flowing through the light emitting diode L increases by a factor of 10 when the input voltage U increases 10 times, for example, and the total power loss of the digital input in this example increases by a factor of 100.
  • FIG second conventional circuit arrangement for a digital input of an electronic device In this case, a current-limiting diode CLD (current limiting diode) replaces the series resistor R v of the circuit arrangement shown in FIG. Order.
  • the constant-current diode CLD stabilizes the electrical current ⁇ rule from a certain stabilization value of the input voltage U by keeping the current at higher input voltages U almost constant.
  • this has the advantage that, starting from the stabilization value, the total power loss of the circuit arrangement only increases linearly with the input voltage U and no longer quadratically as in the case of the circuit arrangement illustrated in FIG.
  • the disadvantage is that commercially available current-regulating diodes CLD tolerate only a maximum supply voltage of about 100 V and thus are not suitable for a larger input voltage range.
  • Figure 3 shows a first embodiment of a circuit arrangement according OF INVENTION ⁇ dung for a digital input of an electronic device.
  • MOSFET M self-conductive metal oxide semiconductor field effect transistor M, hereinafter referred to as MOSFET M, which is arranged between the semiconductor diode D and the zener diode V z ⁇ and the series resistor R v the Darge in Figure 1 ⁇ presented first conventional circuit arrangement or the constant-current diode replaced CLD the embodiment shown in Figure 2 the second conventional circuit arrangement.
  • the MOSFET M has a control terminal G M (gate), a source terminal S M (source), a drain terminal D M (drain) and a substrate terminal B M (bulk) and is formed as an n-channel metal oxide semiconductor field effect transistor ,
  • the drain port D M directly to the semiconductor diode D is verbun ⁇
  • the source terminal S M is connected to the substrate terminal B M
  • the control terminal G M is connected via a current ⁇ control resistor R B to the source terminal S M and di ⁇ rectly with connected to the zener diode V z .
  • the current control resistor R B provides at current flow for ei ⁇ ne negative voltage at the control terminal G M of the MOSFET M and thereby adjusts the current corresponding to the characteristic of MOSFET M on.
  • the MOSFET M thus acts as a dynamic current source of the circuit arrangement.
  • the Zener diode Vz be ⁇ acts as in the conventional circuit arrangements according to Figures 1 and 2 to set a switching threshold of the circuit arrangement, from which it is SENS ⁇ Lich for input signals.
  • the semiconductor diode D protects the electronic circuit from harmful input voltages U.
  • the circuit arrangement shown in FIG. 3 has the advantage that metal oxide semiconductor field effect transistors with relatively high blocking voltages can be obtained and a wide input voltage range can be covered by a circuit arrangement according to FIG. 3, in particular between a DC input voltage U of 24 V up to an AC input voltage U of 230 V.
  • MOSFET M for example, an under
  • another self-conducting field-effect transistor for example a self-conducting junction field-effect transistor, can also be used correspondingly.
  • Figure 4 shows a second embodiment of a circuit arrangement according OF INVENTION ⁇ dung for a digital input egg nes electronic device. It differs from the circuit arrangement shown in Figure 3 only in that the semiconductor diode D is replaced by a bridge rectifier B. Compared to the embodiment illustrated in FIG. 3, this circuit arrangement allows a faster response of the digital input to alternating input voltages U by means of a two-way rectification of the electric current. and is therefore to be preferred to the circuit of Figure 3 in cases where such a rapid response is advantageous.
  • Figure 5 shows a third embodiment of a circuit arrangement according OF INVENTION ⁇ dung for a digital input of an electronic device.
  • This exemplary embodiment is a first embodiment of the circuit arrangement illustrated in FIG. 3 by adding various respectively optional protective elements for protecting the circuit from high or high-frequency input voltages U.
  • These protective elements are a suppressor diode V T , suppression capacitors C x , C Y and at least one additional protection element R z , L z .
  • the suppressor diode V T is arranged in the circuit elekt ⁇ rically between the outputs of the semiconductor diode D and the optocoupler 0 T. It serves to protect against a threshold voltage exceeding input voltages U, which could damage the MOSFET M.
  • Decoupling capacitors C x, C Y are so-called each X or Y capacitors electrically ver to the input of Halbleiterdio- de D, possibly via an additional protecting member R z, L z, and / or to the output of the optocoupler 0 T ⁇ are bound. They protect the circuit from input voltages U whose frequency exceeds a protection frequency.
  • the additional protection elements R z , L z are a protective resistor R z connected upstream of the semiconductor diode D and a ballast protection element L z which is connected upstream of the interference suppression capacitors C x , C Y may be an electrical resistance or an inductive electrical component.
  • the protective resistor R z serves primarily to divide the total power loss on the MOSFET M and the protective resistor R z and thereby relieve the MOSFET M.
  • This third embodiment can be varied by ressordiode depending on the requirements to the circuit arrangement at least one of the decoupling capacitors C x, C Y and / or the Supp- V T and / or at least one of the additional protection ⁇ members R z, L z is omitted.
  • Figure 6 shows a fourth embodiment of a circuit arrangement according OF INVENTION ⁇ dung for a digital input egg nes electronic device, which is a second embodiment of the circuit arrangement shown in FIG. 3
  • a first bypass capacitor C s is electrically connected in parallel with the current control resistor R B.
  • This fourth embodiment is particularly advantageous ⁇ way, when the circuit arrangement for reducing the total power loss of the digital input, a non dargestell ⁇ tes, the digital input Feeding electromechanical relay is connected upstream.
  • the circuit arrangement for reducing the total power loss of the digital input a non dargestell ⁇ tes
  • the digital input Feeding electromechanical relay is connected upstream.
  • FIG. 7 shows a fifth embodiment of a circuit arrangement according OF INVENTION ⁇ dung for a digital input of an electronic device which is a third embodiment of the circuit arrangement shown in FIG.
  • FIG. 8 shows a sixth embodiment of a circuit arrangement according OF INVENTION ⁇ dung for a digital input of an electronic device which is a fourth embodiment of the circuit arrangement shown in FIG.
  • This refinement provides a second bridging capacitor C P i electrically connected in parallel with the light-emitting diode L of the optocoupler O T , a series resistor R V arranged between the semiconductor diode D and the MOSFET M, and a third bypass capacitor C P 2, the third bridging capacitor C P 2
  • the capacitor C P 2 is electrically connected in parallel with the part of the circuit arrangement formed by the MOSFET M, the Zener diode V z and the light-emitting diode L.
  • FIGS. 3 to 8 can also be suitably combined.
  • the semiconductor diode D can be replaced by a bridge rectifier B as in FIG. 4 and / or the exemplary embodiments illustrated in FIGS . 6 to 8 can be used around protective elements V T , C x , C Y , R z and / or L z are expanded as in FIG.

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  • Rectifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit pour une entrée d'un appareil électronique. Le circuit comprend un redresseur pour le redressement d'un flux de courant, un transistor à effet de champ autoconducteur, un organe de blocage pour le blocage du flux de courant en-deçà d'un seuil de commutation d'une tension d'entrée (U), et un organe séparateur pour la séparation galvanique de l'entrée numérique d'au moins un autre composant, de l'appareil électronique, auquel il est couplé.
PCT/EP2011/057512 2010-06-29 2011-05-10 Circuit pour une entrée numérique Ceased WO2012000708A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010030656.8 2010-06-29
DE201010030656 DE102010030656A1 (de) 2010-06-29 2010-06-29 Schaltungsanordnung für einen Digitaleingang

Publications (1)

Publication Number Publication Date
WO2012000708A1 true WO2012000708A1 (fr) 2012-01-05

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Application Number Title Priority Date Filing Date
PCT/EP2011/057512 Ceased WO2012000708A1 (fr) 2010-06-29 2011-05-10 Circuit pour une entrée numérique

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DE (1) DE102010030656A1 (fr)
WO (1) WO2012000708A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103346767A (zh) * 2013-06-28 2013-10-09 清华大学 一种电子开关设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014101353B4 (de) 2014-02-04 2018-01-25 Phoenix Contact Gmbh & Co. Kg Weitbereichs-Eingangsschaltung
DE102016203419B4 (de) 2016-03-02 2017-11-16 Siemens Aktiengesellschaft Kaskadierbare Schaltung für ein Signaleinkopplungssystem
EP4636512A1 (fr) * 2024-04-19 2025-10-22 Siemens Aktiengesellschaft Ensemble d'entrée numérique

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3693060A (en) * 1971-04-13 1972-09-19 Philips Corp Solid-state relay using light-emitting diodes
GB1403110A (en) 1971-07-12 1975-08-13 Eaton Corp Signal isolation system including a phototransistor
US4197471A (en) 1977-09-29 1980-04-08 Texas Instruments Incorporated Circuit for interfacing between an external signal and control apparatus
US4275307A (en) 1978-04-19 1981-06-23 Allen-Bradley Company Input circuit for digital control systems
DE3419227A1 (de) 1984-05-23 1985-11-28 Staiber, Heinrich, 8201 Bad Feilnbach Galvanisch getrennter, microcomputercompatibler schalter fuer wechselstromgroessen
JPH02135819A (ja) 1988-11-16 1990-05-24 Matsushita Electric Works Ltd 光結合型リレー回路
JPH06177736A (ja) 1992-12-10 1994-06-24 Matsushita Electric Works Ltd 固体リレー
JPH0746111A (ja) 1993-07-30 1995-02-14 Matsushita Electric Works Ltd 半導体リレー
US5539352A (en) 1994-12-28 1996-07-23 General Electric Company Low power voltage input circuit with high noise immunity and fast operating time
US5672919A (en) 1995-03-24 1997-09-30 Abb Power T&D Company Inc. Low current binary input subsystem
US5909660A (en) 1994-10-13 1999-06-01 National Instruments Corporation Signal conditioning module for sensing multiform field voltage signals
EP1906533A1 (fr) * 2006-09-29 2008-04-02 Siemens Aktiengesellschaft Circuit d'entrée numérique avec un composant opto-électronique
DE102007025243B3 (de) 2007-05-31 2009-01-08 Siemens Ag Digitale Eingangsschaltung

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3693060A (en) * 1971-04-13 1972-09-19 Philips Corp Solid-state relay using light-emitting diodes
GB1403110A (en) 1971-07-12 1975-08-13 Eaton Corp Signal isolation system including a phototransistor
US4197471A (en) 1977-09-29 1980-04-08 Texas Instruments Incorporated Circuit for interfacing between an external signal and control apparatus
US4275307A (en) 1978-04-19 1981-06-23 Allen-Bradley Company Input circuit for digital control systems
DE3419227A1 (de) 1984-05-23 1985-11-28 Staiber, Heinrich, 8201 Bad Feilnbach Galvanisch getrennter, microcomputercompatibler schalter fuer wechselstromgroessen
JPH02135819A (ja) 1988-11-16 1990-05-24 Matsushita Electric Works Ltd 光結合型リレー回路
JPH06177736A (ja) 1992-12-10 1994-06-24 Matsushita Electric Works Ltd 固体リレー
JPH0746111A (ja) 1993-07-30 1995-02-14 Matsushita Electric Works Ltd 半導体リレー
US5909660A (en) 1994-10-13 1999-06-01 National Instruments Corporation Signal conditioning module for sensing multiform field voltage signals
US5539352A (en) 1994-12-28 1996-07-23 General Electric Company Low power voltage input circuit with high noise immunity and fast operating time
US5672919A (en) 1995-03-24 1997-09-30 Abb Power T&D Company Inc. Low current binary input subsystem
EP1906533A1 (fr) * 2006-09-29 2008-04-02 Siemens Aktiengesellschaft Circuit d'entrée numérique avec un composant opto-électronique
DE102007025243B3 (de) 2007-05-31 2009-01-08 Siemens Ag Digitale Eingangsschaltung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103346767A (zh) * 2013-06-28 2013-10-09 清华大学 一种电子开关设备

Also Published As

Publication number Publication date
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