WO2014154521A2 - Procédé pour produire du cssni3 de phase γ et utilisation du cssni3 de phase γ, du cs1-xaxb1-ycyi3-zxz, du bii3 ou du bi1-xmi3-yxy pour des transistors en couches minces - Google Patents

Procédé pour produire du cssni3 de phase γ et utilisation du cssni3 de phase γ, du cs1-xaxb1-ycyi3-zxz, du bii3 ou du bi1-xmi3-yxy pour des transistors en couches minces Download PDF

Info

Publication number
WO2014154521A2
WO2014154521A2 PCT/EP2014/055358 EP2014055358W WO2014154521A2 WO 2014154521 A2 WO2014154521 A2 WO 2014154521A2 EP 2014055358 W EP2014055358 W EP 2014055358W WO 2014154521 A2 WO2014154521 A2 WO 2014154521A2
Authority
WO
WIPO (PCT)
Prior art keywords
cssn
solution
layer
zxz
printing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2014/055358
Other languages
German (de)
English (en)
Other versions
WO2014154521A3 (fr
Inventor
Felix Eickemeyer
Wilfried HERMES
Daniel WALDMANN
Fabian Seeler
Daniel KÄLBLEIN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BASF SE
Original Assignee
BASF SE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BASF SE filed Critical BASF SE
Publication of WO2014154521A2 publication Critical patent/WO2014154521A2/fr
Publication of WO2014154521A3 publication Critical patent/WO2014154521A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01G—COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G19/00—Compounds of tin
    • C01G19/006—Compounds containing tin, with or without oxygen or hydrogen, and containing two or more other elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/26—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition
    • H10P14/265—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition using solutions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2006/00—Physical properties of inorganic compounds
    • C01P2006/32—Thermal properties
    • C01P2006/33—Phase transition temperatures

Definitions

  • the invention relates to the preparation of ⁇ -cesium-tin-iodide, and to a solvent-based application of ⁇ -cesium-tin-iodide, Csi-xA x Bi- y Cyl3-zXz, bismuth iodide, or Bii-xMy -yXy a substrate and the use as semiconductor material in transistor structures.
  • Thin-film transistors known as TFTs, are widely used as switching elements in electronics, especially for large area applications. Its main application is in the backplane of active-matrix liquid crystal displays (AMLCD) or active-matrix OLED displays (AMOLED). In addition, they are used, for example, in the field of sensors and RFI D systems.
  • amorphous silicon is a cost effective alternative to crystalline silicon for large area applications.
  • the application of amorphous silicon class is limited to devices with low switching speed as its mobility of about 10 "1 cmWS times smaller than that of crystalline silicon approx 15,000.
  • amorphous silicon is less expensive to produce than crystalline silicon, requires the Deposition of amorphous silicon still requires cost-intensive vacuum processes, such as plasma-assisted chemical vapor deposition.Furthermore, the two-dimensional deposition methods subsequently require complex and cost-intensive structuring by lithographic methods, for which a photoresist is usually structured by photolithography and then as Mask used to pattern the a-Si layer.
  • LTPS Low-temperature polysilicon
  • LTPS Low-temperature polysilicon
  • LTPS is produced by a laser treatment of a-Si, which leads to a partial crystallization of the a-Si.
  • LTPS has a number of disadvantages.
  • the laser annealing necessary for the production of LTPS requires high investment costs and complicates the scaling up of the manufacturing process.
  • LTPS has a reduced homogeneity compared to a-Si.
  • compensation circuits and a modified structure of the backplane are usually necessary. This leads to an increase in the required pro- nesssch ritte, an increased process complexity and thus increased production costs compared to back side plates made of a-Si.
  • metal oxides such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • ⁇ 10-30cm 2 / Vs
  • LTPS a number of display prototypes based on IGZO backplane have already been presented.
  • the metal oxide layer has also been deposited extensively by expensive vacuum processes, in particular sputtering, for the previously realized back side plates.
  • a-Si and LTPS and the currently used metal oxides are deposited by complex and cost-intensive vacuum methods (a-Si / LTPS usually by plasma-assisted vapor deposition and metal oxides by sputtering).
  • the semiconductor materials are deposited by these methods over the entire surface of the substrate. For the manufacture of the transistors, therefore, complicated lithographic processes for structuring are necessary following the deposition.
  • organic semiconductors have been studied, for example, in US Pat. No. 5,347,144. Due to the good processability by chemical solution deposition, eg via dripping, spin coating, dip coating, ink jet printing or gravure printing, organic materials offer a low-cost alternative to a-Si, LTPS and metal oxides. In addition, organic materials can be processed from solution at low temperatures, making them compatible with inexpensive and flexible plastic substrates. The mobilities in solution-processed organic materials are in the range of a-Si and in some cases even in the range of 1 to 5 cm 2 / Vs. However, organic semiconductors often have a lack of stability of the electrical properties, which hitherto prevented large-scale use.
  • Solution-processable inorganic materials offer the opportunity to combine the advantages of cost-effective printing methods with the higher intrinsic mobilities of inorganic materials compared to organic materials.
  • Solution-processable metal oxides starting from metal precursors show mobilities of ⁇ 1 -50 cm 2 / Vs in TFTs when the precursors react to metal oxides at temperatures between 300 ° C and 500 ° C.
  • procedures have also been launched which enables TFTs with mobilities in the range of 5 cmWs ⁇ ⁇ 15 cmWs for process temperatures of T ⁇ 200 ° C. This is described inter alia in WO 12/103528 A2 and H. Sirringhaus et al. (Nat. Mat. Vol. 10 (201 1) 45-50).
  • WO 201 1/071738 describes a luminescent material having the following formal structure: [AaS-nbXxX'X'X'V] [dopant], where A is a monovalent cation, where X, X ', and X "are selected from the group fluorine , Chloro, bromo and iodo, where a is between 1 and 5, where b is between 1 and 5 and the sum of ⁇ , ⁇ 'and x "is (a + 2b) and at least X' is iodine.
  • the dopant is preferably present at 0.1 to 1 percent of the elemental composition.
  • the dopant preferably contains oxygen-containing anions, for example O 2- and OH-.
  • the layer containing the luminescent material described is produced by means of the vacuum deposits by evaporation of, for example, stannous iodide and cesium (I) iodide.
  • Kanatzidis et al. (Nature, Vol. 485 (2012) 486-494) also discloses the use of CsSn as a p-type semiconductor in solar cells. Kanatzidis et al. also describes a Hall mobility of CsSn of 585 cm 2 / Vs and that CsSn dissolves in polar solvents such as acetonitrile, methoxy-acetonitrile or DMF and is thus solvent-processable.
  • polar solvents such as acetonitrile, methoxy-acetonitrile or DMF
  • Kanatzidis et al. JACS Vol. 134 (2012) 8579-8587 further discloses that CsSnl 3 is a "unique phase-change material" and has four polymorphs It is described that two polymorphs are stable at room temperature and can be transformed by heat treatment or by It is described that the pure polymorph B- ⁇ can be represented by a reaction of the stoichiometric mixture of tin (II) iodide and cesium (I) iodide at 550 ° C in an evacuated ampoule and subsequent cooling.
  • the pure Y Polymorph can be represented by a reaction of the stoichiometric mixture of tin (II) iodide and cesium (I) iodide in ethylenediamine.
  • the Y polymorph can be converted by temperature treatment at 550 ° C into the polymorph ⁇ - ⁇ .
  • the polymorph ⁇ - ⁇ transforms into the Y polymorph by release in air. First, ⁇ - ⁇ is formed by absorption of atmospheric moisture and then oxidized to Cs2Snl6.
  • the object of the present invention was to demonstrate a simplified manufacturing route for the y-CsSn in comparison with the prior art.
  • a further object of the present invention was to identify materials which are suitable as semiconductors and which can be processed as a thin layer by means of printing methods which represent a cost-effective production variant, the layer thickness typically being in the range from 1 to 1000 nm.
  • Another object of the present invention was to show materials that already at temperatures in the range of max. Form 250 ° C semiconducting layers that can be used as active layers in TFTs.
  • the present invention relates to a process for the solvent-based preparation of ⁇ -CsSn, which is characterized in that (i) Y-CsSn is prepared from solution, wherein the solvent in an inert atmosphere and / or under vacuum at a temperature of 0 ° C. is evaporated to 500 ° C, and (ii) Y-CsSn is converted by heat treatment in the range of 50 to 500 ° C in an inert atmosphere and / or under vacuum in y-CsSn.
  • a reaction space which has a volume of at least 100 ml / g to 1 l / g per gram of Y-CsSn.
  • the reactions (i) and (ii) are advantageously carried out under a nitrogen and / or argon atmosphere and / or under vacuum.
  • steps (i) and / or (ii) are carried out at a pressure of less than 500 mbar, preferably less than 100 mbar, in particular in the range of less than 10 mbar.
  • steps (i) and / or (ii) are carried out at a pressure of less than 500 mbar, preferably less than 100 mbar, in particular in the range of less than 10 mbar.
  • reaction time of both steps (i) and (ii) is advantageously 1 minute to 20 hours, preferably 10 minutes to 2 hours.
  • the presence of water and / or oxygen is advantageously to be kept to a minimum, preferably less than 10000 ppm, in particular completely avoided.
  • Dissolved CsSn can be prepared by any means known to those skilled in the art.
  • Csl + Sn reacts in a melt reaction to form CsSn and the CsSn thus prepared is dissolved in a polar solvent.
  • a polar solvent for example, acetonitrile, a mixture of acetonitrile and dimethylformamide or a mixture of acetonitrile: dimethylformamide: methoxyacetonitrile can be used as the polar solvent.
  • this solution is heated for 1 to 5 hours at about 70 ° C with stirring.
  • the reaction is carried out under an inert atmosphere, for example a nitrogen or argon atmosphere.
  • the present invention furthermore relates to a method for producing a thin layer of semiconducting material, which is characterized in that a CsSn solution, a CsixAxB-i-yCy-zXz solution, a Bi solution or a Bi x M x l3-yXy solution is applied to a substrate by means of printing techniques, wherein the application is carried out under inert atmosphere and / or vacuum using a CsSn solution.
  • the thickness of the layer is advantageously 1 to 1000 nm, preferably 10 to 200 nm, particularly preferably 20 to 100 nm.
  • the layer is homogeneous and closed. Homogeneous is understood to mean that the layer at the point with the smallest thickness is at least 30% of the thickness of the layer at the thickest point, preferably 50%. By closed is meant that the layer covers at least 90% of the underlying surface, preferably at least 95%, in particular at least 98% or completely.
  • the measurement of the layer thickness, the homogeneity and the closeness of the layer is preferably determined by atomic force microscopy, in particular in tapping mode.
  • Suitable printing techniques include spin-coating, drop casting, dip coating, 2D inkjet printing, gravure printing, offset printing, flexoprinting or screen printing, microcontact (microcontact). wave) prin- ing), preferred are continuous printing methods, eg. B. 2D inkjet printing.
  • polar solvents are advantageous, in particular alcohols, ketones, aldehydes, amides, esters, ethers, sulfoxides, lactones, lactams and / or nitriles.
  • acetone and butanone are advantageous.
  • CsSn and CsixAxB-i-yCy -zXz especially DMF
  • acetonitrile, methoxy-acetonitrile, methoxy-isopropanol, DMSO and acetone are particularly advantageous.
  • Bi is commercially available.
  • M stands for tin, germanium, lead or selenium
  • X is chlorine or bromine.
  • x and y can be chosen in all areas known to those skilled in the art.
  • A stands for barium or strontium
  • B is tin, lead or germanium, preferably tin
  • C is bismuth, indium, gallium, silver or antimony
  • X is chlorine or bromine
  • x, y and z can be chosen in all areas known to those skilled in the art.
  • Csi xA x Bi yCyl3-ZXZ and Bii- x M x l3-yXy can be prepared for example by adding the respective components in the melt reaction.
  • the starting materials substituted in solution.
  • any material which is stable under the manufacturing conditions of a thin layer of semiconductive material described below can be used.
  • These may be in particular organic, inorganic and composite materials.
  • examples are glass, quartz glass, metal foils, ceramics, doped and undoped inorganic semiconductors (eg silicon, germanium, etc.), polymeric materials (eg polyacrylates, epoxides, polyamides, polycarbonates, polyimides, polyketones, poly (ether ether ketone), polyethylene naphthalate ( PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS)), paper), in particular glass and plastic.
  • glass, quartz glass, metal foils, ceramics, doped and undoped inorganic semiconductors eg silicon, germanium, etc.
  • polymeric materials eg polyacrylates, epoxides, polyamides, polycarbonates, polyimides, polyketones, poly (ether ether ketone), polyethylene naphthalate (
  • an insulating layer may be deposited on the substrate prior to the application of the semiconducting layer, in particular organic or inorganic dielectrics, in particular oxides (eg silicon oxide, aluminum oxide, titanium oxide, preferably S1O2, Al2O3), nitrides (eg silicon nitride), polymers (eg polyimides, Polyacrylates, polymethyl methacrylates (PMMA), polystyrene, fluoropolymers).
  • oxides eg silicon oxide, aluminum oxide, titanium oxide, preferably S1O2, Al2O3
  • nitrides eg silicon nitride
  • polymers eg polyimides, Polyacrylates, polymethyl methacrylates (PMMA), polystyrene, fluoropolymers.
  • the layer is dried at a temperature of 0 ° C to 500 ° C, preferably at 0 ° C to 250 ° C, especially at 20 ° C to 150 ° C, using a CsSn solution, the drying step under inert Atmosphere and / or vacuum is performed.
  • a temperature in the range from 0 ° C. to 150 ° C., preferably from 20 ° C. to 80 ° C. is advantageously selected for drying.
  • CsSnl 3 or CSI x AxBi-yCyl 3 - zXz is advantageously chosen for drying a temperature in the range of 0 ° C to 350 ° C, preferably 20 ° C to 150 ° C.
  • this drying temperature is maintained for a period of 0.5 to 30 minutes, preferably for a period of 1 to 5 minutes.
  • a further temperature step for increasing the crystalline content may be carried out at a temperature in the range from 20 ° C to 500 ° C, preferably at a temperature in the range from 80 ° C to 250 ° C. If, using CsSn in the first temperature step, the temperature is selected such that Y-CsSn is present after drying, this second temperature step is imperative for converting Y-CsSn into y-CsSn.
  • the temperature is advantageously in the range of 70 to 250 ° C, preferably 120 to 200 ° C, in particular 150 to 180 ° C. Using CsSn, this second temperature step is performed under inert atmosphere and / or vacuum.
  • the present invention further relates to the layer of semiconductive material prepared by the above-described methods.
  • the layer thus produced has a very low concentration of foreign atoms.
  • the inventive method is both suitable for producing y-CsSn as a bulk material and for producing y-CsSn as a thin layer.
  • the present invention further relates to the use of y-CsSn, Csi-xA x Bi- y Cyl3-zXz and Bi and Bi x M x l3-yXy in thin-film transistors.
  • RFID systems and sensors are potential applications for low-cost TFTs.
  • the compounds mentioned are also suitable as hole and electron conductors and absorption material in solar cells and as a luminescent material.
  • y-CsSn and Csi-xA x Bi- y Cyl3 as active sensor material (eg oxygen sensor, air humidity sensor, etc.).
  • the present invention further relates to a transistor comprising: a source region (source contact) and a drain region (drain contact); a channel layer extending between the source region and the drain region, wherein the channel layer of y-CSSN, CsI x A x Bi y CYL3-ZXZ, Bii- x M y Xy or L3 Bib includes x; a gate region (gate electrode) disposed in spaced proximity to the channel layer and an electrically insulating layer (dielectric) between the gate region and the source region, the drain region and the channel layer.
  • organic and inorganic materials can be advantageously used.
  • inorganic dielectrics are silicium oxides, aluminum oxides, titanium oxides, titaniumates, tantalum oxides, tantalates, silicon nitrides, zirconium oxides, zirconates, barium titanate and other dielectrics in perwoskite structure.
  • organic dielectrics are polyimides, polyacrylates, polymethyl methacrylates (PMMA), polystyrene, fluoropolymers, etc.
  • SiO 2 is used as the dielectric.
  • drain contact and the gate electrode advantageously electrically conductive materials are used.
  • conductive polymers eg PEDOT: PSS
  • transparent conductors eg ITO (indium tin oxide), AZO (aluminum doped zinc oxide), graphene, etc.
  • ITO indium tin oxide
  • AZO aluminum doped zinc oxide
  • graphene etc.
  • Preferred transistor geometries are the following:
  • Substrate, dielectric, channel layer preferably gate electrode, dielectric, channel layer, source and drain contact, known as bottom-gate top contact geometry 2.
  • Substrate, dielectric, channel layer preferably substrate, gate electrode, dielectric, source and drain contact, channel layer, known as bottom-gate bottom contact geometry.
  • the present invention enables the preparation of y-CsSn from Y-CsSn or directly from solution at temperatures below 500 ° C, especially at low temperatures below 250 ° C.
  • the invention includes the cost-effective production of thin layers of inorganic semiconductor materials such as B1I3, Bi x x M x l3-yXy 'CsSn or Csi xAxB-i-yCy -zXz by solution-based processes at temperatures below 500 ° C, especially at low Temperatures below 250 ° C.
  • the present invention makes it possible to produce layers with a low concentration of impurities since, apart from the solvent, there are no impurities. This is advantageous in comparison to precursor-based production methods, as are generally used for TFTs based on metal oxides. Care must always be taken in these production processes that the unneeded parts of the precausors are removed as completely as possible from the layer, eg by temperature treatment.
  • the use of inorganic semiconductors also offers the possibility of realizing the combination of high charge carrier mobility with low processing temperatures in TFT applications. Examples
  • Spin coating was used to deposit a Bib layer on an oxidized Si wafer with an oxide thickness of 300 nm.
  • the rotational speed was 1000 rpm and a rotation time of 30 seconds.
  • optical microscopy and atomic force microscopy it was shown that the resulting layer is homogeneous and closed at a thickness d ⁇ 15nm.
  • Example 2 Bib in butanone
  • Bib layers were prepared on oxidized Si wafers. The layers are not closed, but have islands isolated from each other. An electrical conductivity is not possible.
  • Example 5 Gate field dependent current flow through a CsSnb thin film:
  • N, N-dimethylformamide acetonitrile: methoxyacetonitrile (1: 1: 1).
  • a small amount of the solution was dropped on a silicon wafer and allowed to dry.
  • the silicon wafer consisted of highly doped silicon (gate electrode) covered with a 230 nm thick layer of silicon dioxide (gate dielectric), as well as lithographically structured source and drain contacts consisting of a 10 nm thick layer of indium tin oxide (ITO) and a 30 nm thick layer Gold (Au).
  • ITO indium tin oxide
  • Au gold
  • FIG. 1 A schematic layer structure for the electrical characterization is shown in FIG. 1
  • the measurements were on a transistor with a channel length (L) of 10 ⁇ and a channel width (W) of 10000 ⁇ performed.
  • the thickness of the dielectric (S1O2) was 230 nm and had a dielectric constant ⁇ ⁇ of 3.9.
  • the permittivity of the vacuum was 8,85E-12 As / Vm.
  • the area normalized capacitance CG of the dielectric was thus 15 nF / cm 2 .
  • the mobility ⁇ was calculated from the slope of the input characteristics.
  • the slope m was determined by linear regression in the VGs range from 0 V to -40 V.
  • the curves obtained from the linear regression are shown in Figure 4 (solid black lines).
  • FIG. 4 shows the electrical characterization of the dripped CsSn layer
  • Input characteristics measured for drain-source voltages VDS -1 V, -10 V, -20 V, -30 V, - 40 V.
  • the solid black lines were fitted to the input characteristics using linear regression.
  • a CsSn layer was deposited on an oxidized Si wafer having an oxide thickness of 300 nm.
  • the rotation speed was 1000 rpm.
  • optical microscopy and atomic force microscopy it was shown that the resulting layer is homogeneous and closed at a thickness d ⁇ 40 nm.
  • FIG. 7 shows an atomic force microscope image (tapping mode) of the CsSn layer from Example 6.
  • the height difference detected by the color scale is 80 nm.
  • FIG. 8 shows the associated height profile.
  • a thin layer of the material was applied to the surface of a silicon wafer consisting of highly doped silicon (gate electrode) covered with a 300 nm thick layer of silicon dioxide (gate dielectric).
  • gate electrode highly doped silicon
  • gate dielectric silicon dioxide
  • the sample was dried at 150 ° C for 60 minutes on a hot plate. After drying, the layer source and drain contacts through a shadow mask in the vacuum by thermal evaporation are (p ⁇ 10 "6 mbar) is applied.
  • the contacts consisted of a 50 nm thick layer of gold.
  • the measurements were carried out on a transistor with a channel length (L) of 50 ⁇ m and a channel width (W) of 500 ⁇ m.
  • the thickness of the dielectric (S1O2) was 300 nm and had a dielectric constant ⁇ ⁇ of 3.9. 8.85 ⁇ 10.
  • "12 is the permittivity of vacuum ⁇ was As / Vm.
  • the area-normalized capacitance CG of the dielectric thus was 1 1, 5 nF / cm 2, the mobility ⁇ was calculated from the slope of the input characteristics.
  • the slope m was determined by linear regression in the VGS range from 0 V to -40 V determined.
  • FIG. 9 shows the electrical characteristic of the CsSn layer produced as described above.
  • the solid line was adapted to the input characteristics by means of linear regression.
  • the field effect mobility determined with the formula from Example 5 was 2.3 cm 2 / Vs.
  • Example 8 CsSn in Dimethyformamide: acetonitrile: methoxyisopropanol - (1: 1: 1)
  • a CsSn layer was deposited on an oxidized Si wafer having an oxide thickness of 300 nm.
  • the rotation speed was 1000 rpm.
  • optical microscopy and atomic force microscopy it was shown that the resulting layer is homogeneous and closed at a thickness d ⁇ 40 nm. Compared with Example 6, the roughness of the layer could be reduced.
  • FIG. 10 shows an optical microscope image of the CsSn layer from Example 8,
  • FIG. 11 an atomic force microscope image (tapping mode) of the edge region of this layer, wherein the term "height sensor” indicates the height difference of 120 nm recorded with the color scale
  • Figure 12 shows the associated height profile
  • Figure 13 shows an atomic force microscope (tapping mode) image of the higher magnification layer, wherein the height difference detected by the color scale is 25 nm
  • Figure 14 shows the associated elevation profile.
  • a CsSn solution in methanohacetonitrile - (1: 1) was prepared at a concentration of c ⁇ 20 mg / ml.
  • a CsSn layer was deposited on an oxidized Si wafer having an oxide thickness of 300 nm.
  • the rotation speed was 1000 rpm. It was shown by optical microscopy that no closed layer but single CsSn crystals were formed.
  • FIG. 15 shows an optical microscope image of a CsSn layer from Comparative Example 2.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne la production d'iodure de césium-étain de phase γ à partir d'une solution d'iodure de césium-étain, cette solution étant évaporée et l'iodure de césium-étain étant ensuite soumis à un traitement thermique. Elle concerne également l'application, à l'aide d'un solvant, d'iodure de césium-étain de phase γ, de Cs1-xAxB1-yCyI3, de Bi1-xMI3-yXy ou d'iodure de bismuth sur un substrat et leur utilisation comme semi-conducteur dans des structures de transistors. Une solution de CsSnI3, une solution de Cs1-xAxB1-yCyI3-zXz, une solution de Bi1-xMxI3-yXy ou une solution de BiI3 étant déposée sur un substrat au moyen de techniques d'impression. En utilisant une solution de CsSnI3, l'application est réalisée sous atmosphère inerte et/ou sous vide.
PCT/EP2014/055358 2013-03-25 2014-03-18 Procédé pour produire du cssni3 de phase γ et utilisation du cssni3 de phase γ, du cs1-xaxb1-ycyi3-zxz, du bii3 ou du bi1-xmi3-yxy pour des transistors en couches minces Ceased WO2014154521A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP13160850 2013-03-25
EP13160850.7 2013-03-25

Publications (2)

Publication Number Publication Date
WO2014154521A2 true WO2014154521A2 (fr) 2014-10-02
WO2014154521A3 WO2014154521A3 (fr) 2015-02-19

Family

ID=48045271

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2014/055358 Ceased WO2014154521A2 (fr) 2013-03-25 2014-03-18 Procédé pour produire du cssni3 de phase γ et utilisation du cssni3 de phase γ, du cs1-xaxb1-ycyi3-zxz, du bii3 ou du bi1-xmi3-yxy pour des transistors en couches minces

Country Status (2)

Country Link
TW (1) TW201446655A (fr)
WO (1) WO2014154521A2 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8679587B2 (en) * 2005-11-29 2014-03-25 State of Oregon acting by and through the State Board of Higher Education action on Behalf of Oregon State University Solution deposition of inorganic materials and electronic devices made comprising the inorganic materials
US9196482B2 (en) * 2011-06-01 2015-11-24 Kai Shum Solution-based synthesis of CsSnI3

Also Published As

Publication number Publication date
TW201446655A (zh) 2014-12-16
WO2014154521A3 (fr) 2015-02-19

Similar Documents

Publication Publication Date Title
EP2376434B1 (fr) Matériau fonctionnel destiné à des composants électroniques imprimés
Xu et al. Low temperature solution-processed IGZO thin-film transistors
JP4581062B2 (ja) 電界効果トランジスタ、半導体デバイス作製用インク、電界効果トランジスタの製造方法、および有機複素環化合物
Yang et al. Solution-deposited Zr-doped AlO x gate dielectrics enabling high-performance flexible transparent thin film transistors
Xu et al. p-Type transparent amorphous oxide thin-film transistors using low-temperature solution-processed nickel oxide
Xu et al. Solution-processed yttrium oxide dielectric for high-performance IZO thin-film transistors
Xia et al. Sol-gel processed high-k aluminum oxide dielectric films for fully solution-processed low-voltage thin-film transistors
WO2012033073A1 (fr) Matériau semi-conducteur organique, composition semi-conductrice organique, film mince organique, transistor à effet de champ, et procédé de fabrication associé
TWI712602B (zh) 有機半導體組合物及包含其之有機薄膜、與其用途
Zhang et al. Low-temperature and high-performance ZnSnO thin film transistor activated by lightwave irradiation
Kim et al. Controlled Zr doping for inkjet-printed ZTO TFTs
JP5187737B2 (ja) 電界効果トランジスタ、その製造方法及びそれに用いる化合物、並びに半導体デバイス作製用インク
Lee et al. Fabrication of a solution-processed thin-film transistor using zinc oxide nanoparticles and zinc acetate
KR100960808B1 (ko) 산화물 반도체 박막 및 그 제조 방법
Kim et al. Solution-processed semiconducting aluminum-zinc-tin-oxide thin films and their thin-film transistor applications
TWI601212B (zh) 薄膜電晶體及其製造方法、結晶性氧化物半導體薄膜及其製造方法、顯示裝置及ｘ線感測器
Choudhary et al. Study on dielectric properties of PVP and Al2O3 thin films and their implementation in low-temperature solution-processed IGZO-based thin-film transistors
Acharya et al. Solution-processed Pb0. 8Ba0. 2ZrO3 as a gate dielectric for low-voltage metal-oxide thin-film transistor
US20230268443A1 (en) Thin film transistor and preparation method thereof
WO2014154521A2 (fr) Procédé pour produire du cssni3 de phase γ et utilisation du cssni3 de phase γ, du cs1-xaxb1-ycyi3-zxz, du bii3 ou du bi1-xmi3-yxy pour des transistors en couches minces
CN106967045B (zh) 杂并苯化合物的中间体、使用其的杂并苯化合物的合成方法
Zhang et al. Low-temperature solution-processed alumina dielectric films for low-voltage organic thin film transistors
JP7083106B2 (ja) 有機半導体組成物及びその用途
KR101139162B1 (ko) 클러스터 화합물을 이용한 칼코게나이드 박막의 형성방법
CN111373514A (zh) 氧化物半导体薄膜

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14710576

Country of ref document: EP

Kind code of ref document: A2

122 Ep: pct application non-entry in european phase

Ref document number: 14710576

Country of ref document: EP

Kind code of ref document: A2