ATE141424T1 - Vorrichtung und technik für burstprogrammierung - Google Patents

Vorrichtung und technik für burstprogrammierung

Info

Publication number
ATE141424T1
ATE141424T1 AT89306134T AT89306134T ATE141424T1 AT E141424 T1 ATE141424 T1 AT E141424T1 AT 89306134 T AT89306134 T AT 89306134T AT 89306134 T AT89306134 T AT 89306134T AT E141424 T1 ATE141424 T1 AT E141424T1
Authority
AT
Austria
Prior art keywords
burst
column latch
counter
memory
memory controller
Prior art date
Application number
AT89306134T
Other languages
English (en)
Inventor
Percy P Aria
David W Stoenner
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE141424T1 publication Critical patent/ATE141424T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
  • Programmable Controllers (AREA)
  • Processing Of Color Television Signals (AREA)
AT89306134T 1988-06-24 1989-06-16 Vorrichtung und technik für burstprogrammierung ATE141424T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/211,357 US5134699A (en) 1988-06-24 1988-06-24 Programmable burst data transfer apparatus and technique

Publications (1)

Publication Number Publication Date
ATE141424T1 true ATE141424T1 (de) 1996-08-15

Family

ID=22786599

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89306134T ATE141424T1 (de) 1988-06-24 1989-06-16 Vorrichtung und technik für burstprogrammierung

Country Status (7)

Country Link
US (1) US5134699A (de)
EP (1) EP0348113B1 (de)
JP (1) JP2992552B2 (de)
AT (1) ATE141424T1 (de)
DE (1) DE68926936T2 (de)
ES (1) ES2090037T3 (de)
GR (1) GR3020706T3 (de)

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CA2118662C (en) * 1993-03-22 1999-07-13 Paul A. Santeler Memory controller having all dram address and control signals provided synchronously from a single device
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US5590286A (en) * 1993-10-07 1996-12-31 Sun Microsystems, Inc. Method and apparatus for the pipelining of data during direct memory accesses
JP3579461B2 (ja) 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
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JP3155144B2 (ja) * 1994-03-25 2001-04-09 ローム株式会社 データ転送方法及び装置
US5701433A (en) * 1994-10-14 1997-12-23 Compaq Computer Corporation Computer system having a memory controller which performs readahead operations which can be aborted prior to completion
US5598569A (en) * 1994-10-17 1997-01-28 Motorola Inc. Data processor having operating modes selected by at least one mask option bit and method therefor
US5644788A (en) * 1994-10-28 1997-07-01 Cyrix Corporation Burst transfers using an ascending or descending only burst ordering
US5787267A (en) * 1995-06-07 1998-07-28 Monolithic System Technology, Inc. Caching method and circuit for a memory system with circuit module architecture
US6470405B2 (en) * 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US5802597A (en) * 1995-12-22 1998-09-01 Cirrus Logic, Inc. SDRAM memory controller while in burst four mode supporting single data accesses
US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6243768B1 (en) 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6006288A (en) * 1996-06-06 1999-12-21 Motorola, Inc. Method and apparatus for adaptable burst chip select in a data processing system
US5774135A (en) * 1996-11-05 1998-06-30 Vlsi, Technology, Inc. Non-contiguous memory location addressing scheme
US6055619A (en) * 1997-02-07 2000-04-25 Cirrus Logic, Inc. Circuits, system, and methods for processing multiple data streams
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6457075B1 (en) * 1999-05-17 2002-09-24 Koninkijke Philips Electronics N.V. Synchronous memory system with automatic burst mode switching as a function of the selected bus master
US6611796B1 (en) * 1999-10-20 2003-08-26 Texas Instruments Incorporated Method and apparatus for combining memory blocks for in circuit emulation
US6477610B1 (en) 2000-02-04 2002-11-05 International Business Machines Corporation Reordering responses on a data bus based on size of response
US6580659B1 (en) * 2000-08-25 2003-06-17 Micron Technology, Inc. Burst read addressing in a non-volatile memory device
US6449203B1 (en) * 2001-03-08 2002-09-10 Micron Technology, Inc. Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
US6751159B2 (en) 2001-10-26 2004-06-15 Micron Technology, Inc. Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
US6838331B2 (en) * 2002-04-09 2005-01-04 Micron Technology, Inc. Method and system for dynamically operating memory in a power-saving error correction mode
US6751143B2 (en) * 2002-04-11 2004-06-15 Micron Technology, Inc. Method and system for low power refresh of dynamic random access memories
US7149824B2 (en) * 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
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Also Published As

Publication number Publication date
JP2992552B2 (ja) 1999-12-20
DE68926936D1 (de) 1996-09-19
ES2090037T3 (es) 1996-10-16
JPH0266662A (ja) 1990-03-06
GR3020706T3 (en) 1996-11-30
EP0348113A3 (de) 1991-09-11
EP0348113A2 (de) 1989-12-27
US5134699A (en) 1992-07-28
EP0348113B1 (de) 1996-08-14
DE68926936T2 (de) 1997-02-27

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee