ATE162924T1 - Verfahren zur herstellung von metallisierten löchern in dielektrischen substraten mit untereinander verbundenen dünnschichtleiter- und/oder widerstandsbahnen - Google Patents

Verfahren zur herstellung von metallisierten löchern in dielektrischen substraten mit untereinander verbundenen dünnschichtleiter- und/oder widerstandsbahnen

Info

Publication number
ATE162924T1
ATE162924T1 AT94117039T AT94117039T ATE162924T1 AT E162924 T1 ATE162924 T1 AT E162924T1 AT 94117039 T AT94117039 T AT 94117039T AT 94117039 T AT94117039 T AT 94117039T AT E162924 T1 ATE162924 T1 AT E162924T1
Authority
AT
Austria
Prior art keywords
paths
thin film
gold
deposition
dielectric substrates
Prior art date
Application number
AT94117039T
Other languages
English (en)
Inventor
Massimo Bertolotti
Giorgio Carcano
Anna Carminati
Maurizio Ceriani
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IT93MI002697A external-priority patent/IT1265414B1/it
Priority claimed from IT93MI002698A external-priority patent/IT1265415B1/it
Application filed by Italtel Spa filed Critical Italtel Spa
Application granted granted Critical
Publication of ATE162924T1 publication Critical patent/ATE162924T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors incorporating printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
AT94117039T 1993-12-22 1994-10-27 Verfahren zur herstellung von metallisierten löchern in dielektrischen substraten mit untereinander verbundenen dünnschichtleiter- und/oder widerstandsbahnen ATE162924T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT93MI002697A IT1265414B1 (it) 1993-12-22 1993-12-22 Processo per la realizzazione di fori metallizzati in substrati dielettrici comprendenti percorsi conduttivi e/o resistivi in film
IT93MI002698A IT1265415B1 (it) 1993-12-22 1993-12-22 Processo per la realizzazione di fori metallizzati in substrati dielettrici comprendenti percorsi conduttivi e/o resistivi in film

Publications (1)

Publication Number Publication Date
ATE162924T1 true ATE162924T1 (de) 1998-02-15

Family

ID=26331076

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94117039T ATE162924T1 (de) 1993-12-22 1994-10-27 Verfahren zur herstellung von metallisierten löchern in dielektrischen substraten mit untereinander verbundenen dünnschichtleiter- und/oder widerstandsbahnen

Country Status (3)

Country Link
EP (1) EP0670668B1 (de)
AT (1) ATE162924T1 (de)
DE (1) DE69408298D1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1279080B1 (it) * 1995-11-29 1997-12-04 Sits Soc It Telecom Siemens Processo di fabbricazione di circuiti in film sottile comprendenti condensatori integrati
DE19961683A1 (de) * 1999-12-21 2001-06-28 Philips Corp Intellectual Pty Bauteil mit Dünnschichtschaltkreis
CN102946691B (zh) * 2012-11-07 2015-04-29 东莞生益电子有限公司 含局部金属化的台阶开槽的pcb板制作方法
CN105578801B (zh) * 2015-12-15 2018-04-03 深圳崇达多层线路板有限公司 一种阻焊油墨半塞孔的背钻孔的制作方法
CN119450903B (zh) * 2023-08-03 2025-11-14 庆鼎精密电子（淮安）有限公司 具有金属化半孔的电路板及其制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4226932A (en) * 1979-07-05 1980-10-07 Gte Automatic Electric Laboratories Incorporated Titanium nitride as one layer of a multi-layered coating intended to be etched
US4402998A (en) * 1982-01-04 1983-09-06 Western Electric Co., Inc. Method for providing an adherent electroless metal coating on an epoxy surface
DE3524832A1 (de) * 1985-07-11 1987-01-15 Siemens Ag Herstellung von duennfilmschaltungen
IT1191680B (it) * 1986-03-19 1988-03-23 Gte Telecom Spa Processo per la realizzazione di fori metallizzati in un substrato dotato di cammini conduttivi e resistivi,e prodotto ottenuto con il processo suddetto
IT1216135B (it) * 1988-03-18 1990-02-22 Sits Soc It Telecom Siemens Dielettrico mediante deposizioni in processo per la realizzazione di vuoto di metalli, e relativo fori metallizzati in un substrato prodotto ottenuto.

Also Published As

Publication number Publication date
EP0670668B1 (de) 1998-01-28
EP0670668A1 (de) 1995-09-06
DE69408298D1 (de) 1998-03-05

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Legal Events

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