ATE170011T1 - Einrichtung zur aktualisierung von programmzählern - Google Patents
Einrichtung zur aktualisierung von programmzählernInfo
- Publication number
- ATE170011T1 ATE170011T1 AT95303671T AT95303671T ATE170011T1 AT E170011 T1 ATE170011 T1 AT E170011T1 AT 95303671 T AT95303671 T AT 95303671T AT 95303671 T AT95303671 T AT 95303671T AT E170011 T1 ATE170011 T1 AT E170011T1
- Authority
- AT
- Austria
- Prior art keywords
- program counter
- less significant
- counter circuit
- execute
- fetch
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Debugging And Monitoring (AREA)
- Stored Programmes (AREA)
- Image Processing (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/252,030 US5559975A (en) | 1994-06-01 | 1994-06-01 | Program counter update mechanism |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE170011T1 true ATE170011T1 (de) | 1998-09-15 |
Family
ID=22954326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT95303671T ATE170011T1 (de) | 1994-06-01 | 1995-05-30 | Einrichtung zur aktualisierung von programmzählern |
Country Status (5)
| Country | Link |
|---|---|
| US (4) | US5559975A (de) |
| EP (1) | EP0685788B1 (de) |
| JP (1) | JP3628379B2 (de) |
| AT (1) | ATE170011T1 (de) |
| DE (1) | DE69504135T2 (de) |
Families Citing this family (68)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07200289A (ja) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | 情報処理装置 |
| US5819057A (en) * | 1995-01-25 | 1998-10-06 | Advanced Micro Devices, Inc. | Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units |
| US5708788A (en) * | 1995-03-03 | 1998-01-13 | Fujitsu, Ltd. | Method for adjusting fetch program counter in response to the number of instructions fetched and issued |
| US5819059A (en) * | 1995-04-12 | 1998-10-06 | Advanced Micro Devices, Inc. | Predecode unit adapted for variable byte-length instruction set processors and method of operating the same |
| WO1996038783A1 (en) * | 1995-06-01 | 1996-12-05 | Hal Computer Systems, Inc. | Method and apparatus for rotating active instructions in a parallel data processor |
| US5875315A (en) * | 1995-06-07 | 1999-02-23 | Advanced Micro Devices, Inc. | Parallel and scalable instruction scanning unit |
| US7301541B2 (en) | 1995-08-16 | 2007-11-27 | Microunity Systems Engineering, Inc. | Programmable processor and method with wide operations |
| US5854921A (en) * | 1995-08-31 | 1998-12-29 | Advanced Micro Devices, Inc. | Stride-based data address prediction structure |
| US5752069A (en) * | 1995-08-31 | 1998-05-12 | Advanced Micro Devices, Inc. | Superscalar microprocessor employing away prediction structure |
| US5835747A (en) * | 1996-01-26 | 1998-11-10 | Advanced Micro Devices, Inc. | Hierarchical scan logic for out-of-order load/store execution control |
| US6038657A (en) * | 1995-10-06 | 2000-03-14 | Advanced Micro Devices, Inc. | Scan chains for out-of-order load/store execution control |
| US5872947A (en) * | 1995-10-24 | 1999-02-16 | Advanced Micro Devices, Inc. | Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions |
| US5787241A (en) * | 1995-12-18 | 1998-07-28 | Integrated Device Technology, Inc. | Method and apparatus for locating exception correction routines |
| US5930489A (en) * | 1996-02-09 | 1999-07-27 | Advanced Micro Devices, Inc. | Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructions sets |
| US5961580A (en) * | 1996-02-20 | 1999-10-05 | Advanced Micro Devices, Inc. | Apparatus and method for efficiently calculating a linear address in a microprocessor |
| US5790826A (en) * | 1996-03-19 | 1998-08-04 | S3 Incorporated | Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes |
| US5835968A (en) * | 1996-04-17 | 1998-11-10 | Advanced Micro Devices, Inc. | Apparatus for providing memory and register operands concurrently to functional units |
| US6085302A (en) * | 1996-04-17 | 2000-07-04 | Advanced Micro Devices, Inc. | Microprocessor having address generation units for efficient generation of memory operation addresses |
| EP0896700A1 (de) * | 1996-05-01 | 1999-02-17 | Advanced Micro Devices, Inc. | Superskalarer mikroprozessor mit hochleistungseinheit zur befehlsausrichtung |
| EP0919025B1 (de) * | 1996-07-16 | 2001-09-26 | Advanced Micro Devices, Inc. | Parallele und skalierbare befehlsabtasteinheit |
| US5867680A (en) * | 1996-07-24 | 1999-02-02 | Advanced Micro Devices, Inc. | Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions |
| US6049863A (en) * | 1996-07-24 | 2000-04-11 | Advanced Micro Devices, Inc. | Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor |
| US6370636B1 (en) | 1996-07-31 | 2002-04-09 | Hyundai Electronics Industries Co., Ltd. | Accessing byte lines from dual memory blocks and aligning for variable length instruction execution |
| DE19634031A1 (de) * | 1996-08-23 | 1998-02-26 | Siemens Ag | Prozessor mit Pipelining-Aufbau |
| US5889975A (en) * | 1996-11-07 | 1999-03-30 | Intel Corporation | Method and apparatus permitting the use of a pipe stage having an unknown depth with a single microprocessor core |
| US5852727A (en) * | 1997-03-10 | 1998-12-22 | Advanced Micro Devices, Inc. | Instruction scanning unit for locating instructions via parallel scanning of start and end byte information |
| US6289437B1 (en) * | 1997-08-27 | 2001-09-11 | International Business Machines Corporation | Data processing system and method for implementing an efficient out-of-order issue mechanism |
| US6167506A (en) * | 1997-11-17 | 2000-12-26 | Advanced Micro Devices, Inc. | Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location |
| US6134649A (en) * | 1997-11-17 | 2000-10-17 | Advanced Micro Devices, Inc. | Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction |
| US6108774A (en) * | 1997-12-19 | 2000-08-22 | Advanced Micro Devices, Inc. | Branch prediction with added selector bits to increase branch prediction capacity and flexibility with minimal added bits |
| US6061786A (en) * | 1998-04-23 | 2000-05-09 | Advanced Micro Devices, Inc. | Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction |
| EP0953898A3 (de) * | 1998-04-28 | 2003-03-26 | Matsushita Electric Industrial Co., Ltd. | Prozessor zur Ausführung von Befehlen aus dem Speicher mittels eines Programmzählers und Kompiler, Assembler, Programmverbinder und Fehlerbeseitiger für einen solchen Prozessor |
| US6175908B1 (en) | 1998-04-30 | 2001-01-16 | Advanced Micro Devices, Inc. | Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte |
| US6141745A (en) * | 1998-04-30 | 2000-10-31 | Advanced Micro Devices, Inc. | Functional bit identifying a prefix byte via a particular state regardless of type of instruction |
| ATE557342T1 (de) * | 1998-08-24 | 2012-05-15 | Microunity Systems Eng | Prozessor und verfahren zur matrixmultiplikation mit einem breiten operand |
| US6393527B1 (en) * | 1998-12-18 | 2002-05-21 | Ati International Srl | Prefetch buffer with continue detect |
| US6038660A (en) * | 1999-05-26 | 2000-03-14 | Infineon Technologies North America Corp. | Method and apparatus for updating a program counter |
| US6438664B1 (en) | 1999-10-27 | 2002-08-20 | Advanced Micro Devices, Inc. | Microcode patch device and method for patching microcode using match registers and patch routines |
| US6918028B1 (en) * | 2000-03-28 | 2005-07-12 | Analog Devices, Inc. | Pipelined processor including a loosely coupled side pipe |
| US6874081B2 (en) * | 2001-05-17 | 2005-03-29 | Broadcom Corporation | Selection of link and fall-through address using a bit in a branch address for the selection |
| US20040167786A1 (en) * | 2002-03-08 | 2004-08-26 | Grace John J. | System for optimizing selection of a college or a university and a method for utilizing the system provided by a program |
| TW588243B (en) * | 2002-07-31 | 2004-05-21 | Trek 2000 Int Ltd | System and method for authentication |
| US7877581B2 (en) * | 2002-12-12 | 2011-01-25 | Pmc-Sierra Us, Inc. | Networked processor for a pipeline architecture |
| US6957319B1 (en) | 2003-02-19 | 2005-10-18 | Advanced Micro Devices, Inc. | Integrated circuit with multiple microcode ROMs |
| US20050050278A1 (en) * | 2003-09-03 | 2005-03-03 | Advanced Micro Devices, Inc. | Low power way-predicted cache |
| US7117290B2 (en) * | 2003-09-03 | 2006-10-03 | Advanced Micro Devices, Inc. | MicroTLB and micro tag for reducing power in a processor |
| US7281120B2 (en) * | 2004-03-26 | 2007-10-09 | International Business Machines Corporation | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor |
| US7649879B2 (en) * | 2004-03-30 | 2010-01-19 | Extreme Networks, Inc. | Pipelined packet processor |
| US7889750B1 (en) * | 2004-04-28 | 2011-02-15 | Extreme Networks, Inc. | Method of extending default fixed number of processing cycles in pipelined packet processor architecture |
| US20060149931A1 (en) * | 2004-12-28 | 2006-07-06 | Akkary Haitham | Runahead execution in a central processing unit |
| US7822033B1 (en) | 2005-12-30 | 2010-10-26 | Extreme Networks, Inc. | MAC address detection device for virtual routers |
| US7817633B1 (en) | 2005-12-30 | 2010-10-19 | Extreme Networks, Inc. | Method of providing virtual router functionality through abstracted virtual identifiers |
| US7894451B2 (en) * | 2005-12-30 | 2011-02-22 | Extreme Networks, Inc. | Method of providing virtual router functionality |
| KR20070101998A (ko) * | 2006-04-13 | 2007-10-18 | 한국과학기술원 | 마이크로 컨트롤러의 프로그램 카운터 및 그 제어방법 |
| US8035650B2 (en) * | 2006-07-25 | 2011-10-11 | Qualcomm Incorporated | Tiled cache for multiple software programs |
| US7852486B2 (en) * | 2008-02-07 | 2010-12-14 | Board Of Regents, The University Of Texas System | Wavelength and intensity monitoring of optical cavity |
| US8495699B2 (en) * | 2008-12-23 | 2013-07-23 | At&T Intellectual Property I, L.P. | Distributed content analysis network |
| US20100223673A1 (en) * | 2009-02-27 | 2010-09-02 | At&T Intellectual Property I, L.P. | Providing multimedia content with access restrictions |
| US20100223660A1 (en) * | 2009-02-27 | 2010-09-02 | At&T Intellectual Property I, L.P. | Providing multimedia content with time limit restrictions |
| KR101059899B1 (ko) * | 2009-04-23 | 2011-08-29 | 광주과학기술원 | 마이크로 프로세서 |
| US8904421B2 (en) | 2009-06-30 | 2014-12-02 | At&T Intellectual Property I, L.P. | Shared multimedia experience including user input |
| US8605732B2 (en) | 2011-02-15 | 2013-12-10 | Extreme Networks, Inc. | Method of providing virtual router functionality |
| US9785565B2 (en) | 2014-06-30 | 2017-10-10 | Microunity Systems Engineering, Inc. | System and methods for expandably wide processor instructions |
| US10198260B2 (en) | 2016-01-13 | 2019-02-05 | Oracle International Corporation | Processing instruction control transfer instructions |
| US10061580B2 (en) | 2016-02-25 | 2018-08-28 | International Business Machines Corporation | Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence |
| US10719248B2 (en) | 2018-04-20 | 2020-07-21 | Micron Technology, Inc. | Apparatuses and methods for counter update operations |
| CN112233715B (zh) * | 2019-07-15 | 2024-06-18 | 美光科技公司 | 用于存储器系统的维护操作 |
| CN114741117B (zh) * | 2022-03-09 | 2024-08-09 | 上交所技术有限责任公司 | 一种跨平台的程序指令重排的验证方法 |
Family Cites Families (47)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3781808A (en) * | 1972-10-17 | 1973-12-25 | Ibm | Virtual memory system |
| US3875391A (en) * | 1973-11-02 | 1975-04-01 | Raytheon Co | Pipeline signal processor |
| AT354159B (de) * | 1975-02-10 | 1979-12-27 | Siemens Ag | Assoziativspeicher mit getrennt assoziierbaren bereichen |
| US4155119A (en) * | 1977-09-21 | 1979-05-15 | Sperry Rand Corporation | Method for providing virtual addressing for externally specified addressed input/output operations |
| US4179737A (en) * | 1977-12-23 | 1979-12-18 | Burroughs Corporation | Means and methods for providing greater speed and flexibility of microinstruction sequencing |
| US4200912A (en) * | 1978-07-31 | 1980-04-29 | Motorola, Inc. | Processor interrupt system |
| US4384343A (en) * | 1979-02-12 | 1983-05-17 | Honeywell Information Systems Inc. | Firmware controlled search and verify apparatus and method for a data processing system |
| US4453212A (en) * | 1981-07-13 | 1984-06-05 | Burroughs Corporation | Extended address generating apparatus and method |
| US4807115A (en) * | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
| FR2554952B1 (fr) * | 1983-11-15 | 1989-04-28 | Telecommunications Sa | Procede et systeme d'adressage pour memoire dynamique |
| JPH0658631B2 (ja) * | 1983-12-19 | 1994-08-03 | 株式会社日立製作所 | デ−タ処理装置 |
| US4685078A (en) * | 1984-10-31 | 1987-08-04 | International Business Machines Corporation | Dual incrementor |
| US5133062A (en) * | 1986-03-06 | 1992-07-21 | Advanced Micro Devices, Inc. | RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory |
| AU587714B2 (en) * | 1986-08-27 | 1989-08-24 | Amdahl Corporation | Cache storage queue |
| US4853889A (en) * | 1986-09-03 | 1989-08-01 | American Telephone And Telegraph Company, At&T Bell Laboratories | Arrangement and method for speeding the operation of branch instructions |
| US5131086A (en) * | 1988-08-25 | 1992-07-14 | Edgcore Technology, Inc. | Method and system for executing pipelined three operand construct |
| US5056006A (en) * | 1988-09-12 | 1991-10-08 | General Electric Company | Parallel processor with single program storage and sequencer and simultaneous instruction processing |
| US5051885A (en) * | 1988-10-07 | 1991-09-24 | Hewlett-Packard Company | Data processing system for concurrent dispatch of instructions to multiple functional units |
| US5113515A (en) * | 1989-02-03 | 1992-05-12 | Digital Equipment Corporation | Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer |
| US5067069A (en) * | 1989-02-03 | 1991-11-19 | Digital Equipment Corporation | Control of multiple functional units with parallel operation in a microcoded execution unit |
| US5155816A (en) * | 1989-02-10 | 1992-10-13 | Intel Corporation | Pipelined apparatus and method for controlled loading of floating point data in a microprocessor |
| US5155820A (en) * | 1989-02-21 | 1992-10-13 | Gibson Glenn A | Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits |
| US5226126A (en) * | 1989-02-24 | 1993-07-06 | Nexgen Microsystems | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags |
| CA2016068C (en) * | 1989-05-24 | 2000-04-04 | Robert W. Horst | Multiple instruction issue computer architecture |
| US5136697A (en) * | 1989-06-06 | 1992-08-04 | Advanced Micro Devices, Inc. | System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache |
| US5471593A (en) * | 1989-12-11 | 1995-11-28 | Branigin; Michael H. | Computer processor with an efficient means of executing many instructions simultaneously |
| US5185871A (en) * | 1989-12-26 | 1993-02-09 | International Business Machines Corporation | Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions |
| US5546551A (en) * | 1990-02-14 | 1996-08-13 | Intel Corporation | Method and circuitry for saving and restoring status information in a pipelined computer |
| US5226130A (en) * | 1990-02-26 | 1993-07-06 | Nexgen Microsystems | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency |
| JP2822588B2 (ja) * | 1990-04-30 | 1998-11-11 | 日本電気株式会社 | キャッシュメモリ装置 |
| ATE146611T1 (de) * | 1990-05-04 | 1997-01-15 | Ibm | Maschinenarchitektur für skalaren verbundbefehlssatz |
| CA2037708C (en) * | 1990-05-04 | 1998-01-20 | Richard J. Eickemeyer | General purpose compound apparatus for instruction-level parallel processors |
| CA2045773A1 (en) * | 1990-06-29 | 1991-12-30 | Compaq Computer Corporation | Byte-compare operation for high-performance processor |
| US5325499A (en) * | 1990-09-28 | 1994-06-28 | Tandon Corporation | Computer system including a write protection circuit for preventing illegal write operations and a write poster with improved memory |
| US5261063A (en) * | 1990-12-07 | 1993-11-09 | Ibm Corp. | Pipeline apparatus having pipeline mode eecuting instructions from plural programs and parallel mode executing instructions from one of the plural programs |
| KR100299691B1 (ko) * | 1991-07-08 | 2001-11-22 | 구사마 사부로 | 확장가능알아이에스씨마이크로프로세서구조 |
| JPH0820949B2 (ja) * | 1991-11-26 | 1996-03-04 | 松下電器産業株式会社 | 情報処理装置 |
| DE69311330T2 (de) * | 1992-03-31 | 1997-09-25 | Seiko Epson Corp., Tokio/Tokyo | Befehlsablauffolgeplanung von einem risc-superskalarprozessor |
| US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
| US5367650A (en) * | 1992-07-31 | 1994-11-22 | Intel Corporation | Method and apparauts for parallel exchange operation in a pipelined processor |
| US5450560A (en) * | 1992-12-21 | 1995-09-12 | Motorola, Inc. | Pointer for use with a buffer and method of operation |
| US5467473A (en) * | 1993-01-08 | 1995-11-14 | International Business Machines Corporation | Out of order instruction load and store comparison |
| US5465373A (en) * | 1993-01-08 | 1995-11-07 | International Business Machines Corporation | Method and system for single cycle dispatch of multiple instructions in a superscalar processor system |
| US5454117A (en) * | 1993-08-25 | 1995-09-26 | Nexgen, Inc. | Configurable branch prediction for a processor performing speculative execution |
| IE80854B1 (en) * | 1993-08-26 | 1999-04-07 | Intel Corp | Processor ordering consistency for a processor performing out-of-order instruction execution |
| US5574928A (en) * | 1993-10-29 | 1996-11-12 | Advanced Micro Devices, Inc. | Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments |
| DE69429061T2 (de) * | 1993-10-29 | 2002-07-18 | Advanced Micro Devices, Inc. | Superskalarmikroprozessoren |
-
1994
- 1994-06-01 US US08/252,030 patent/US5559975A/en not_active Expired - Lifetime
-
1995
- 1995-05-30 EP EP95303671A patent/EP0685788B1/de not_active Expired - Lifetime
- 1995-05-30 DE DE69504135T patent/DE69504135T2/de not_active Expired - Lifetime
- 1995-05-30 AT AT95303671T patent/ATE170011T1/de not_active IP Right Cessation
- 1995-05-31 JP JP13401195A patent/JP3628379B2/ja not_active Expired - Fee Related
-
1996
- 1996-09-23 US US08/716,764 patent/US5799162A/en not_active Expired - Lifetime
-
1998
- 1998-02-10 US US09/037,436 patent/US6035386A/en not_active Expired - Lifetime
-
2000
- 2000-01-14 US US09/483,493 patent/US6351801B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69504135D1 (de) | 1998-09-24 |
| JPH07334361A (ja) | 1995-12-22 |
| EP0685788A1 (de) | 1995-12-06 |
| US6351801B1 (en) | 2002-02-26 |
| US5799162A (en) | 1998-08-25 |
| US5559975A (en) | 1996-09-24 |
| EP0685788B1 (de) | 1998-08-19 |
| US6035386A (en) | 2000-03-07 |
| JP3628379B2 (ja) | 2005-03-09 |
| DE69504135T2 (de) | 1999-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE170011T1 (de) | Einrichtung zur aktualisierung von programmzählern | |
| DE69233412D1 (de) | Vorrichtung und Rechnerprogrammprodukt zur Ausführung von Verzweigungsbefehlen | |
| DE60038976D1 (de) | Registersatz zur verwendung in einer parallellen mehrfachdrahtprozessorarchitektur | |
| EP1229440A3 (de) | Programmumsetzungseinheit und verbesserter Prozessor für Adressierung | |
| DE69638299D1 (de) | Verfahren und Vorrichtung zur Änderung der Namen von Registern | |
| RU96118510A (ru) | Отображение с помощью мультинаборов команд | |
| ATE85713T1 (de) | Digitalprozessorsteuerung. | |
| NO983266L (no) | Distribuert Behandling | |
| ATE219843T1 (de) | Datenverarbeitungsschaltungen und -schnittstellen | |
| ATE162897T1 (de) | Verfahren und gerät zur beschleunigung von verzweigungsbefehlen | |
| DE69518114D1 (de) | Echtzeittaktschaltung | |
| DE69425870D1 (de) | Entwicklungseinheit mit Vorrichtung zur Regelung der Entwicklermenge | |
| ATE224558T1 (de) | Adressengenerator und verfahren zur indirekten adressierung in einem einzigen zyklus | |
| FI970262A0 (fi) | Ihmis/kone rajapinta tietojenkäsittelylaitteistoille | |
| KR910005570A (ko) | 프로그래머블 서브프레임 방식의 pwm회로 | |
| JPS5423343A (en) | Microprogram controller | |
| ATE63175T1 (de) | Verfahren zur schnellen division langer operanden in datenverarbeitungsanlagen und schaltungsanordnung zur durchfuehrung des verfahrens. | |
| JPS5674762A (en) | Memory unit | |
| EP0446833A3 (en) | Display control apparatus enabling clear display of operation performance of an arithmetic processor | |
| JPS6437623A (en) | Data processor | |
| JPS55131851A (en) | Microprogram controller | |
| JPS5537645A (en) | Microcomputer circuit | |
| JPS6476225A (en) | Coprocessor system | |
| JPS642102A (en) | Program controller | |
| JPS5421144A (en) | Microprogram control unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |