ATE179812T1 - Gerät und verfahren zum starten eines mehrprozessorsystems mit einer global/lokalspeicherarchitektur - Google Patents

Gerät und verfahren zum starten eines mehrprozessorsystems mit einer global/lokalspeicherarchitektur

Info

Publication number
ATE179812T1
ATE179812T1 AT93308706T AT93308706T ATE179812T1 AT E179812 T1 ATE179812 T1 AT E179812T1 AT 93308706 T AT93308706 T AT 93308706T AT 93308706 T AT93308706 T AT 93308706T AT E179812 T1 ATE179812 T1 AT E179812T1
Authority
AT
Austria
Prior art keywords
processor
global memory
booting
reset
global
Prior art date
Application number
AT93308706T
Other languages
English (en)
Inventor
William Rudolph Hardell Jr
James Dodd Henson Jr
Oscar Reid Mitchell
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE179812T1 publication Critical patent/ATE179812T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17375One dimensional, e.g. linear array, ring
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4403Processor initialisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT93308706T 1992-10-30 1993-11-01 Gerät und verfahren zum starten eines mehrprozessorsystems mit einer global/lokalspeicherarchitektur ATE179812T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/969,596 US5448716A (en) 1992-10-30 1992-10-30 Apparatus and method for booting a multiple processor system having a global/local memory architecture

Publications (1)

Publication Number Publication Date
ATE179812T1 true ATE179812T1 (de) 1999-05-15

Family

ID=25515723

Family Applications (1)

Application Number Title Priority Date Filing Date
AT93308706T ATE179812T1 (de) 1992-10-30 1993-11-01 Gerät und verfahren zum starten eines mehrprozessorsystems mit einer global/lokalspeicherarchitektur

Country Status (6)

Country Link
US (1) US5448716A (de)
EP (1) EP0602791B1 (de)
JP (1) JPH06231097A (de)
AT (1) ATE179812T1 (de)
CA (1) CA2099413C (de)
DE (1) DE69324778T2 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3679813B2 (ja) * 1991-07-22 2005-08-03 株式会社日立製作所 並列計算機
DE4426001A1 (de) * 1994-07-22 1996-02-01 Sel Alcatel Ag Verfahren zur Überlastvermeidung bei einem Systemanlauf eines Mehrrechnersystems und Mehrrechnersystem dafür
GB9422854D0 (en) * 1994-11-12 1995-01-04 Int Computers Ltd High availability data processing system
JPH08194679A (ja) * 1995-01-19 1996-07-30 Texas Instr Japan Ltd ディジタル信号処理方法及び装置並びにメモリセル読出し方法
EP0817998A4 (de) * 1995-03-31 1998-09-23 Intel Corp Testen des speichers in einem mehrprozessor-computersystem
JP4226085B2 (ja) 1996-10-31 2009-02-18 株式会社ルネサステクノロジ マイクロプロセッサ及びマルチプロセッサシステム
KR100240572B1 (ko) * 1996-12-05 2000-01-15 윤종용 프로그램 메모리를 공유하는 멀티 프로세서 시스템
JP3180728B2 (ja) * 1997-07-25 2001-06-25 日本電気株式会社 半導体記憶装置
US6058475A (en) * 1997-09-22 2000-05-02 Ncr Corporation Booting method for multi-processor computer
US20050060549A1 (en) * 1998-10-26 2005-03-17 Microsoft Corporation Controlling access to content based on certificates and access predicates
US7174457B1 (en) * 1999-03-10 2007-02-06 Microsoft Corporation System and method for authenticating an operating system to a central processing unit, providing the CPU/OS with secure storage, and authenticating the CPU/OS to a third party
US7194092B1 (en) * 1998-10-26 2007-03-20 Microsoft Corporation Key-based secure storage
US6701429B1 (en) * 1998-12-03 2004-03-02 Telefonaktiebolaget Lm Ericsson(Publ) System and method of start-up in efficient way for multi-processor systems based on returned identification information read from pre-determined memory location
US6601165B2 (en) * 1999-03-26 2003-07-29 Hewlett-Packard Company Apparatus and method for implementing fault resilient booting in a multi-processor system by using a flush command to control resetting of the processors and isolating failed processors
JP4144990B2 (ja) * 2000-01-14 2008-09-03 富士通株式会社 データ処理システム及び初期化方法
US6487464B1 (en) * 2000-02-25 2002-11-26 Intel Corporation Power-on software for robust boot
US6584560B1 (en) 2000-04-19 2003-06-24 Dell Usa, L.P. Method and system for booting a multiprocessor computer
US6782440B2 (en) 2000-07-26 2004-08-24 T.N.S. Holdings, Inc. Resource locking and thread synchronization in a multiprocessor environment
US6665777B2 (en) 2000-07-26 2003-12-16 Tns Holdings, Inc. Method, apparatus, network, and kit for multiple block sequential memory management
US6675277B2 (en) 2000-07-26 2004-01-06 Tns Holdings, Inc. Method and apparatus for demand usable adapter memory access management
US6892298B2 (en) 2000-07-26 2005-05-10 Times N Systems, Inc. Load/store micropacket handling system
US6715059B2 (en) 2000-07-26 2004-03-30 Tas Holdings, Inc. Methods and systems for a shared memory unit with extendable functions
US20020029334A1 (en) * 2000-07-26 2002-03-07 West Karlon K. High availability shared memory system
AU2002302563A1 (en) * 2001-05-19 2002-12-03 International Business Machines Corporation Electronic system and method for booting of an electronic system
US6948079B2 (en) * 2001-12-26 2005-09-20 Intel Corporation Method and apparatus for providing supply voltages for a processor
US7032106B2 (en) 2001-12-27 2006-04-18 Computer Network Technology Corporation Method and apparatus for booting a microprocessor
US20030126477A1 (en) * 2001-12-28 2003-07-03 Zhang Kevin X. Method and apparatus for controlling a supply voltage to a processor
US7487365B2 (en) * 2002-04-17 2009-02-03 Microsoft Corporation Saving and retrieving data based on symmetric key encryption
US7890771B2 (en) 2002-04-17 2011-02-15 Microsoft Corporation Saving and retrieving data based on public key encryption
US7100034B2 (en) * 2003-05-23 2006-08-29 Hewlett-Packard Development Company, L.P. System for selecting another processor to be the boot strap processor when the default boot strap processor does not have local memory
WO2007091297A1 (ja) * 2006-02-06 2007-08-16 Fujitsu Limited 情報処理装置、cpu、診断プログラムおよび診断方法
US7702893B1 (en) * 2006-09-22 2010-04-20 Altera Corporation Integrated circuits with configurable initialization data memory addresses
US7711941B2 (en) * 2006-12-19 2010-05-04 Lsi Corporation Method and apparatus for booting independent operating systems in a multi-processor core integrated circuit
US7814301B2 (en) * 2007-04-11 2010-10-12 Hewlett-Packard Development Company, L.P. Clock architecture for multi-processor systems
US8862922B2 (en) * 2010-01-14 2014-10-14 International Business Machines Corporation Data center power adjustment
US9037838B1 (en) 2011-09-30 2015-05-19 Emc Corporation Multiprocessor messaging system
JP2017135762A (ja) * 2014-06-03 2017-08-03 三菱電機株式会社 圧力タンク、これを用いたガス絶縁開閉装置および圧力タンクの製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4377000A (en) * 1980-05-05 1983-03-15 Westinghouse Electric Corp. Automatic fault detection and recovery system which provides stability and continuity of operation in an industrial multiprocessor control
US4590556A (en) * 1983-01-17 1986-05-20 Tandy Corporation Co-processor combination
US4594657A (en) * 1983-04-22 1986-06-10 Motorola, Inc. Semaphore for memory shared by two asynchronous microcomputers
US4827401A (en) * 1984-10-24 1989-05-02 International Business Machines Corporation Method and apparatus for synchronizing clocks prior to the execution of a flush operation
JPS61281352A (ja) * 1985-06-07 1986-12-11 Hitachi Ltd マルチプロセツサシステムの起動方式
JPS61288262A (ja) * 1985-06-17 1986-12-18 Hitachi Ltd マルチプロセツサシステム
JPH0821025B2 (ja) * 1986-09-29 1996-03-04 株式会社東芝 マルチプロセッサシステムおよび同システムの初期化方法
JPH0766368B2 (ja) * 1986-10-21 1995-07-19 日新電機株式会社 ブ−トプロセツサ決定方式
DE3639571A1 (de) * 1986-11-20 1988-06-01 Standard Elektrik Lorenz Ag Verfahren und schaltungsanordnung zum urladen eines zweitrechners
CA1320276C (en) * 1987-09-04 1993-07-13 William F. Bruckert Dual rail processors with error checking on i/o reads
US5050072A (en) * 1988-06-17 1991-09-17 Modular Computer Systems, Inc. Semaphore memory to reduce common bus contention to global memory with localized semaphores in a multiprocessor system
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5276828A (en) * 1989-03-01 1994-01-04 Digital Equipment Corporation Methods of maintaining cache coherence and processor synchronization in a multiprocessor system using send and receive instructions
US5204938A (en) * 1989-05-30 1993-04-20 Loral Aerospace Corp. Method of implementing a neural network on a digital computer
US5068780A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
IL93239A (en) * 1990-02-01 1993-03-15 Technion Res & Dev Foundation High flow-rate synchronizer/schedular apparatus for multiprocessors

Also Published As

Publication number Publication date
CA2099413C (en) 1999-02-16
CA2099413A1 (en) 1994-05-01
DE69324778T2 (de) 1999-12-09
EP0602791A2 (de) 1994-06-22
US5448716A (en) 1995-09-05
DE69324778D1 (de) 1999-06-10
EP0602791B1 (de) 1999-05-06
JPH06231097A (ja) 1994-08-19
EP0602791A3 (de) 1997-03-19

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