ATE195034T1 - Verfahren zur programmierung einer halbleiterspeicheranordnung - Google Patents

Verfahren zur programmierung einer halbleiterspeicheranordnung

Info

Publication number
ATE195034T1
ATE195034T1 AT96111221T AT96111221T ATE195034T1 AT E195034 T1 ATE195034 T1 AT E195034T1 AT 96111221 T AT96111221 T AT 96111221T AT 96111221 T AT96111221 T AT 96111221T AT E195034 T1 ATE195034 T1 AT E195034T1
Authority
AT
Austria
Prior art keywords
gate
programming
floating gate
semiconductor memory
electron injection
Prior art date
Application number
AT96111221T
Other languages
English (en)
Inventor
Houdt Jan Van
Guido Groeseneken
Herman Maes
Original Assignee
Imec Inter Uni Micro Electr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec Inter Uni Micro Electr filed Critical Imec Inter Uni Micro Electr
Application granted granted Critical
Publication of ATE195034T1 publication Critical patent/ATE195034T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
AT96111221T 1991-01-31 1992-01-30 Verfahren zur programmierung einer halbleiterspeicheranordnung ATE195034T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BE9100091A BE1004424A3 (nl) 1991-01-31 1991-01-31 Transistorstruktuur voor uitwisbare en programmeerbare geheugens.

Publications (1)

Publication Number Publication Date
ATE195034T1 true ATE195034T1 (de) 2000-08-15

Family

ID=3885316

Family Applications (2)

Application Number Title Priority Date Filing Date
AT96111221T ATE195034T1 (de) 1991-01-31 1992-01-30 Verfahren zur programmierung einer halbleiterspeicheranordnung
AT92870016T ATE144651T1 (de) 1991-01-31 1992-01-30 Transistorstruktur für löschbare und programmierbare halbleiterspeicheranordnungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT92870016T ATE144651T1 (de) 1991-01-31 1992-01-30 Transistorstruktur für löschbare und programmierbare halbleiterspeicheranordnungen

Country Status (8)

Country Link
EP (2) EP0501941B1 (de)
JP (1) JP3236054B2 (de)
KR (1) KR100280051B1 (de)
AT (2) ATE195034T1 (de)
BE (1) BE1004424A3 (de)
DE (2) DE69214688T2 (de)
DK (1) DK0501941T3 (de)
ES (2) ES2095453T3 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212541A (en) * 1991-04-18 1993-05-18 National Semiconductor Corporation Contactless, 5v, high speed eprom/flash eprom array utilizing cells programmed using source side injection
US6243293B1 (en) 1992-01-29 2001-06-05 Interuniversitair Micro-Elektronica Centrum Contacted cell array configuration for erasable and programmable semiconductor memories
US6009013A (en) * 1992-01-29 1999-12-28 Interuniversitair Micro-Elektronica Centrum Vzw Contactless array configuration for semiconductor memories
ATE213562T1 (de) * 1995-08-11 2002-03-15 Imec Inter Uni Micro Electr Verfahren zum programmieren einer flash-eeprom- speicherzelle unter optimierung des niedrigen leistungsverbrauchs und verfahren zum löschen dieser zelle
KR100217900B1 (ko) * 1996-04-01 1999-09-01 김영환 플래쉬 메모리 셀의 프로그램 방법
DE69705837T2 (de) * 1996-06-14 2001-11-08 Infineon Technologies Ag Anordnung und verfahren zum speichern und lesen von mehrpegelladung
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
WO2010114406A1 (ru) * 2009-03-30 2010-10-07 Murashev Viktor Nikolaevich Ячейка памяти для быстродействующего эсппзу и способ ее программирования
CN105957806B (zh) * 2016-06-08 2018-05-04 天津大学 用于减少非易失性存储器中数据残留的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958868A (ja) * 1982-09-28 1984-04-04 Nec Corp 半導体不揮発性メモリ
JPS59161873A (ja) * 1983-03-07 1984-09-12 Agency Of Ind Science & Technol 半導体不揮発性メモリ
JPS609168A (ja) * 1983-06-29 1985-01-18 Toshiba Corp 不揮発性半導体メモリ装置
JPS6288368A (ja) * 1985-10-15 1987-04-22 Seiko Instr & Electronics Ltd 半導体不揮発性メモリ
US4794565A (en) * 1986-09-15 1988-12-27 The Regents Of The University Of California Electrically programmable memory device employing source side injection
JPS6393158A (ja) * 1986-10-07 1988-04-23 Toshiba Corp 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
JP3236054B2 (ja) 2001-12-04
ES2095453T3 (es) 1997-02-16
KR100280051B1 (ko) 2001-02-01
ATE144651T1 (de) 1996-11-15
BE1004424A3 (nl) 1992-11-17
DE69214688D1 (de) 1996-11-28
EP0740306A2 (de) 1996-10-30
DE69231300T2 (de) 2001-03-01
EP0501941B1 (de) 1996-10-23
DK0501941T3 (da) 1997-04-01
ES2150053T3 (es) 2000-11-16
DE69214688T2 (de) 1997-04-24
JPH0582794A (ja) 1993-04-02
KR920015561A (ko) 1992-08-27
DE69231300D1 (de) 2000-08-31
EP0740306B1 (de) 2000-07-26
EP0740306A3 (de) 1996-11-13
EP0501941A1 (de) 1992-09-02

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
EELA Cancelled due to lapse of time