ATE207689T1 - Verfahren zur herstellung von abstandshaltern auf einer elektrischen leiterplatte - Google Patents

Verfahren zur herstellung von abstandshaltern auf einer elektrischen leiterplatte

Info

Publication number
ATE207689T1
ATE207689T1 AT96402845T AT96402845T ATE207689T1 AT E207689 T1 ATE207689 T1 AT E207689T1 AT 96402845 T AT96402845 T AT 96402845T AT 96402845 T AT96402845 T AT 96402845T AT E207689 T1 ATE207689 T1 AT E207689T1
Authority
AT
Austria
Prior art keywords
circuit board
plating
electrical circuit
printed circuit
studs
Prior art date
Application number
AT96402845T
Other languages
English (en)
Inventor
Joris Antonia Francisc Peeters
Louis Joseph Vandam
Koenraad Juliaan Georg Allaert
Ann Marie Ackaert
Calster Andre Van
Maria Eugenie Andre Vereeken
Suixin Zhang
Baets Joahn De
Bart Leo Alfons Ma Vandervelde
Original Assignee
Cit Alcatel
Imec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel, Imec filed Critical Cit Alcatel
Application granted granted Critical
Publication of ATE207689T1 publication Critical patent/ATE207689T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
AT96402845T 1996-12-20 1996-12-20 Verfahren zur herstellung von abstandshaltern auf einer elektrischen leiterplatte ATE207689T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96402845A EP0849983B1 (de) 1996-12-20 1996-12-20 Verfahren zur Herstellung von Abstandshaltern auf einer elektrischen Leiterplatte

Publications (1)

Publication Number Publication Date
ATE207689T1 true ATE207689T1 (de) 2001-11-15

Family

ID=8225361

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96402845T ATE207689T1 (de) 1996-12-20 1996-12-20 Verfahren zur herstellung von abstandshaltern auf einer elektrischen leiterplatte

Country Status (9)

Country Link
US (1) US6036836A (de)
EP (1) EP0849983B1 (de)
JP (1) JP3618997B2 (de)
KR (1) KR19980064450A (de)
CN (1) CN1199532C (de)
AT (1) ATE207689T1 (de)
CA (1) CA2222857C (de)
DE (1) DE69620273T2 (de)
ES (1) ES2164226T3 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7244677B2 (en) 1998-02-04 2007-07-17 Semitool. Inc. Method for filling recessed micro-structures with metallization in the production of a microelectronic device
US6632292B1 (en) * 1998-03-13 2003-10-14 Semitool, Inc. Selective treatment of microelectronic workpiece surfaces
TWI223678B (en) * 1998-03-20 2004-11-11 Semitool Inc Process for applying a metal structure to a workpiece, the treated workpiece and a solution for electroplating copper
US6197181B1 (en) * 1998-03-20 2001-03-06 Semitool, Inc. Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece
US6565729B2 (en) * 1998-03-20 2003-05-20 Semitool, Inc. Method for electrochemically depositing metal on a semiconductor workpiece
TW511264B (en) 1999-02-18 2002-11-21 Seiko Epson Corp Semiconductor device, mounting substrate and its manufacturing method, circuit substrate and electronic machine
US6582581B1 (en) * 2000-05-12 2003-06-24 Shipley Company, L.L.C. Sequential build circuit board plating process
KR20030075824A (ko) * 2002-03-21 2003-09-26 주식회사 심텍 테일리스 패턴을 갖는 반도체 패키지용 인쇄회로기판의제조방법
KR20030075825A (ko) * 2002-03-21 2003-09-26 주식회사 심텍 테일리스 패턴을 갖는 반도체 패키지용 인쇄회로기판의제조방법
US7025866B2 (en) * 2002-08-21 2006-04-11 Micron Technology, Inc. Microelectronic workpiece for electrochemical deposition processing and methods of manufacturing and using such microelectronic workpieces
KR100499003B1 (ko) * 2002-12-12 2005-07-01 삼성전기주식회사 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법
EP1435765A1 (de) * 2003-01-03 2004-07-07 Ultratera Corporation Verfahren zur Bildung von Verbindungen auf einem Leitermuster auf einer gedruckten Schaltungsplatte
US20050092611A1 (en) * 2003-11-03 2005-05-05 Semitool, Inc. Bath and method for high rate copper deposition
US7578945B2 (en) * 2004-09-27 2009-08-25 Lam Research Corporation Method and apparatus for tuning a set of plasma processing steps
US7138067B2 (en) * 2004-09-27 2006-11-21 Lam Research Corporation Methods and apparatus for tuning a set of plasma processing steps
EP1784063A1 (de) * 2005-11-08 2007-05-09 Alcatel Lucent Leiterplatte mit darauf montierten mikroelektronischen Komponenten und Verfahren zur Herstellung einer solchen Leiterplatte
TWI315658B (en) * 2007-03-02 2009-10-01 Phoenix Prec Technology Corp Warp-proof circuit board structure
US20080264774A1 (en) * 2007-04-25 2008-10-30 Semitool, Inc. Method for electrochemically depositing metal onto a microelectronic workpiece
US9017540B2 (en) * 2010-06-17 2015-04-28 Viasystems Technologies Corp. L.L.C. Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards
CN116230552B (zh) * 2023-01-09 2025-05-20 圆周率半导体(南通)有限公司 一种用于fcbga的mlo的加工方法及其产品

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016050A (en) * 1975-05-12 1977-04-05 Bell Telephone Laboratories, Incorporated Conduction system for thin film and hybrid integrated circuits
KR900002315A (ko) * 1988-07-19 1990-02-28 더 리젠츠 오브 더 유니버시티 오브 캘리포니아 격리전송라인 및 그것의 형성방법
US5017509A (en) * 1988-07-19 1991-05-21 Regents Of The University Of California Stand-off transmission lines and method for making same
US4946563A (en) * 1988-12-12 1990-08-07 General Electric Company Process for manufacturing a selective plated board for surface mount components
JPH02310941A (ja) * 1989-05-26 1990-12-26 Mitsui Mining & Smelting Co Ltd バンプを有するプリント回路基板およびバンプの形成方法
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5283948A (en) * 1991-05-31 1994-02-08 Cray Research, Inc. Method of manufacturing interconnect bumps
US5261593A (en) * 1992-08-19 1993-11-16 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
WO1995005675A1 (en) * 1993-08-17 1995-02-23 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
JPH07193166A (ja) * 1993-11-19 1995-07-28 Citizen Watch Co Ltd 半田バンプ付き半導体装置及びその製造方法
JPH07273439A (ja) * 1994-03-31 1995-10-20 Du Pont Kk 半田バンプ形成方法
US5525204A (en) * 1994-09-29 1996-06-11 Motorola, Inc. Method for fabricating a printed circuit for DCA semiconductor chips

Also Published As

Publication number Publication date
DE69620273T2 (de) 2002-07-18
JP3618997B2 (ja) 2005-02-09
EP0849983A1 (de) 1998-06-24
CN1195262A (zh) 1998-10-07
EP0849983B1 (de) 2001-10-24
JPH10224014A (ja) 1998-08-21
CN1199532C (zh) 2005-04-27
DE69620273D1 (de) 2002-05-02
KR19980064450A (ko) 1998-10-07
ES2164226T3 (es) 2002-02-16
CA2222857A1 (en) 1998-06-20
US6036836A (en) 2000-03-14
CA2222857C (en) 2004-07-20

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