ATE420461T1 - Verfahren zum herstellen von zusammengesetzten wafern - Google Patents

Verfahren zum herstellen von zusammengesetzten wafern

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Publication number
ATE420461T1
ATE420461T1 AT04292655T AT04292655T ATE420461T1 AT E420461 T1 ATE420461 T1 AT E420461T1 AT 04292655 T AT04292655 T AT 04292655T AT 04292655 T AT04292655 T AT 04292655T AT E420461 T1 ATE420461 T1 AT E420461T1
Authority
AT
Austria
Prior art keywords
donor substrate
substrate
initial
initial donor
compound material
Prior art date
Application number
AT04292655T
Other languages
English (en)
Inventor
Frederic Dupont
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE420461T1 publication Critical patent/ATE420461T1/de

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12Preparing bulk and homogeneous wafers
    • H10P90/16Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/93Ternary or quaternary semiconductor comprised of elements from three different groups, e.g. I-III-V
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/933Germanium or silicon or Ge-Si on III-V

Landscapes

  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)
AT04292655T 2004-11-09 2004-11-09 Verfahren zum herstellen von zusammengesetzten wafern ATE420461T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04292655A EP1667223B1 (de) 2004-11-09 2004-11-09 Verfahren zum Herstellen von zusammengesetzten Wafern

Publications (1)

Publication Number Publication Date
ATE420461T1 true ATE420461T1 (de) 2009-01-15

Family

ID=34931512

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04292655T ATE420461T1 (de) 2004-11-09 2004-11-09 Verfahren zum herstellen von zusammengesetzten wafern

Country Status (9)

Country Link
US (3) US7531428B2 (de)
EP (2) EP1667223B1 (de)
JP (1) JP4489671B2 (de)
KR (1) KR100746182B1 (de)
CN (2) CN100426459C (de)
AT (1) ATE420461T1 (de)
DE (1) DE602004018951D1 (de)
SG (1) SG122972A1 (de)
TW (2) TWI367544B (de)

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US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate

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DE602004018951D1 (de) 2009-02-26
KR100746182B1 (ko) 2007-08-03
TWI367544B (en) 2012-07-01
CN101221895B (zh) 2014-04-23
EP1962340A2 (de) 2008-08-27
US7968909B2 (en) 2011-06-28
EP1667223A1 (de) 2006-06-07
US20110049528A1 (en) 2011-03-03
EP1667223B1 (de) 2009-01-07
JP4489671B2 (ja) 2010-06-23
EP1962340A3 (de) 2009-12-23
SG122972A1 (en) 2006-06-29
US7851330B2 (en) 2010-12-14
CN100426459C (zh) 2008-10-15
US20090191719A1 (en) 2009-07-30
JP2006140445A (ja) 2006-06-01
KR20060052446A (ko) 2006-05-19
US7531428B2 (en) 2009-05-12
CN101221895A (zh) 2008-07-16
US20060099776A1 (en) 2006-05-11
TWI303842B (en) 2008-12-01
CN1790620A (zh) 2006-06-21
TW200616014A (en) 2006-05-16

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