ATE492029T1 - Strukturen für mikroelektronik und mikrosystem sowie herstellungsverfahren - Google Patents

Strukturen für mikroelektronik und mikrosystem sowie herstellungsverfahren

Info

Publication number
ATE492029T1
ATE492029T1 AT05801275T AT05801275T ATE492029T1 AT E492029 T1 ATE492029 T1 AT E492029T1 AT 05801275 T AT05801275 T AT 05801275T AT 05801275 T AT05801275 T AT 05801275T AT E492029 T1 ATE492029 T1 AT E492029T1
Authority
AT
Austria
Prior art keywords
layer
microsystems
microelectronics
structures
manufacturing methods
Prior art date
Application number
AT05801275T
Other languages
English (en)
Inventor
Bernard Aspar
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE492029T1 publication Critical patent/ATE492029T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00595—Control etch selectivity
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Weting (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)
  • Silicon Polymers (AREA)
  • Inorganic Insulating Materials (AREA)
  • Laminated Bodies (AREA)
  • Solid-Sorbent Or Filter-Aiding Compositions (AREA)
AT05801275T 2004-09-30 2005-09-27 Strukturen für mikroelektronik und mikrosystem sowie herstellungsverfahren ATE492029T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0452217A FR2875947B1 (fr) 2004-09-30 2004-09-30 Nouvelle structure pour microelectronique et microsysteme et procede de realisation
US67380105P 2005-04-22 2005-04-22
PCT/EP2005/054854 WO2006035031A1 (en) 2004-09-30 2005-09-27 New structure for microelectronics and microsystem and manufacturing process

Publications (1)

Publication Number Publication Date
ATE492029T1 true ATE492029T1 (de) 2011-01-15

Family

ID=34952707

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05801275T ATE492029T1 (de) 2004-09-30 2005-09-27 Strukturen für mikroelektronik und mikrosystem sowie herstellungsverfahren

Country Status (9)

Country Link
US (2) US20080036039A1 (de)
EP (1) EP1794789B1 (de)
JP (3) JP2008514441A (de)
KR (1) KR100860546B1 (de)
CN (2) CN102637626A (de)
AT (1) ATE492029T1 (de)
DE (1) DE602005025375D1 (de)
FR (1) FR2875947B1 (de)
WO (1) WO2006035031A1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
US20060276008A1 (en) * 2005-06-02 2006-12-07 Vesa-Pekka Lempinen Thinning
FR2897982B1 (fr) * 2006-02-27 2008-07-11 Tracit Technologies Sa Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat
FR2932923B1 (fr) 2008-06-23 2011-03-25 Commissariat Energie Atomique Substrat heterogene comportant une couche sacrificielle et son procede de realisation.
FR2932789B1 (fr) 2008-06-23 2011-04-15 Commissariat Energie Atomique Procede de fabrication d'une structure electromecanique comportant au moins un pilier de renfort mecanique.
FR2932788A1 (fr) 2008-06-23 2009-12-25 Commissariat Energie Atomique Procede de fabrication d'un composant electromecanique mems / nems.
US7927975B2 (en) * 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8637381B2 (en) * 2011-10-17 2014-01-28 International Business Machines Corporation High-k dielectric and silicon nitride box region
US9481566B2 (en) 2012-07-31 2016-11-01 Soitec Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices
WO2014064873A1 (ja) * 2012-10-22 2014-05-01 シャープ株式会社 半導体装置の製造方法
CN104944361B (zh) * 2014-03-25 2016-05-18 中芯国际集成电路制造(北京)有限公司 一种mems器件的制作方法
CN106348245B (zh) * 2015-07-23 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置
CN105895575B (zh) * 2016-05-09 2018-09-25 中国科学院上海微系统与信息技术研究所 一种图形化绝缘体上硅衬底材料及其制备方法
CN108190828B (zh) * 2018-02-07 2024-08-13 北京先通康桥医药科技有限公司 Mems传感器线阵、触诊探头及其制造方法
CN108682661A (zh) * 2018-04-17 2018-10-19 中芯集成电路（宁波）有限公司 一种soi基底及soi基底的形成方法
FR3086096B1 (fr) 2018-09-14 2021-08-27 Soitec Silicon On Insulator Procede de realisation d'un substrat avance pour une integration hybride
FR3091032B1 (fr) * 2018-12-20 2020-12-11 Soitec Silicon On Insulator Procédé de transfert d’une couche superficielle sur des cavités
US10981780B2 (en) 2019-08-19 2021-04-20 Infineon Technologies Ag Membrane support for dual backplate transducers
DE102021213259A1 (de) 2021-11-25 2023-05-25 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Cavity SOI Substrats und mikromechanischen Strukturen darin

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184843A (ja) 1985-02-13 1986-08-18 Toshiba Corp 複合半導体装置とその製造方法
FR2579809B1 (fr) * 1985-04-02 1987-05-15 Thomson Csf Procede de realisation de matrices decommande a diodes pour ecran plat de visualisation electro-optique et ecran plat realise par ce procede
NL8800847A (nl) * 1988-04-05 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een soi-struktuur.
US4956314A (en) * 1989-05-30 1990-09-11 Motorola, Inc. Differential etching of silicon nitride
JPH088231B2 (ja) * 1989-10-02 1996-01-29 大日本スクリーン製造株式会社 絶縁膜の選択的除去方法
JPH0476951A (ja) * 1990-07-18 1992-03-11 Fujitsu Ltd 半導体装置の製造方法および半導体装置
US5376233A (en) * 1992-02-10 1994-12-27 Texas Instruments Incorporated Method for selectively etching oxides
JP3367113B2 (ja) * 1992-04-27 2003-01-14 株式会社デンソー 加速度センサ
JPH06302834A (ja) * 1993-04-09 1994-10-28 Fujikura Ltd 薄膜構造の製造方法
US5393692A (en) * 1993-07-28 1995-02-28 Taiwan Semiconductor Manufacturing Company Recessed side-wall poly plugged local oxidation
JP3181174B2 (ja) * 1994-06-08 2001-07-03 キヤノン株式会社 マイクロ構造体の形成方法
US5658698A (en) * 1994-01-31 1997-08-19 Canon Kabushiki Kaisha Microstructure, process for manufacturing thereof and devices incorporating the same
US5466630A (en) * 1994-03-21 1995-11-14 United Microelectronics Corp. Silicon-on-insulator technique with buried gap
JPH08105748A (ja) * 1994-10-06 1996-04-23 Murata Mfg Co Ltd 角速度センサ、その共振周波数調整方法及びその製造方法
JP3182301B2 (ja) * 1994-11-07 2001-07-03 キヤノン株式会社 マイクロ構造体及びその形成法
JP3430771B2 (ja) * 1996-02-05 2003-07-28 株式会社デンソー 半導体力学量センサの製造方法
JPH10290036A (ja) * 1997-04-11 1998-10-27 Nissan Motor Co Ltd 表面マイクロマシンの製造方法
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JPH1131825A (ja) * 1997-07-10 1999-02-02 Denso Corp 半導体力学量センサの製造方法
JP4144047B2 (ja) * 1997-08-20 2008-09-03 株式会社デンソー 半導体基板の製造方法
US5976945A (en) 1997-11-20 1999-11-02 Vanguard International Semiconductor Corporation Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
US5972758A (en) * 1997-12-04 1999-10-26 Intel Corporation Pedestal isolated junction structure and method of manufacture
JP4032476B2 (ja) * 1997-12-25 2008-01-16 日産自動車株式会社 微小装置の製造方法
JP3424550B2 (ja) * 1998-04-13 2003-07-07 株式会社デンソー 半導体力学量センサの製造方法
JP4787412B2 (ja) * 1999-03-30 2011-10-05 シチズンホールディングス株式会社 薄膜基板の形成方法およびその方法によって形成された薄膜基板
US6335292B1 (en) * 1999-04-15 2002-01-01 Micron Technology, Inc. Method of controlling striations and CD loss in contact oxide etch
FR2795554B1 (fr) * 1999-06-28 2003-08-22 France Telecom Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs
US6716722B1 (en) * 1999-07-15 2004-04-06 Shin-Etsu Handotai Co., Ltd. Method of producing a bonded wafer and the bonded wafer
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
US6372657B1 (en) * 2000-08-31 2002-04-16 Micron Technology, Inc. Method for selective etching of oxides
DE10064494A1 (de) * 2000-12-22 2002-07-04 Bosch Gmbh Robert Verfahren zur Herstellung eines Halbleiterbauelements sowie ein nach dem Verfahren hergestelltes Halbleiterbauelement, wobei das Halbleiterbauelement insbesondere eine bewegliche Masse aufweist
DE10124038A1 (de) * 2001-05-16 2002-11-21 Atmel Germany Gmbh Verfahren zur Herstellung vergrabener Bereiche
US6835633B2 (en) * 2002-07-24 2004-12-28 International Business Machines Corporation SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer
ATE388480T1 (de) * 2002-08-26 2008-03-15 Ibm Membranakivierter mikroelektromechanischer schalter
TWI242796B (en) * 2002-09-04 2005-11-01 Canon Kk Substrate and manufacturing method therefor
FR2847077B1 (fr) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
JP4007172B2 (ja) * 2002-12-03 2007-11-14 ソニー株式会社 マイクロマシンおよびその製造方法
FR2849269B1 (fr) * 2002-12-20 2005-07-29 Soitec Silicon On Insulator Procede de realisation de cavites dans une plaque de silicium
ATE415703T1 (de) * 2002-12-20 2008-12-15 Soitec Silicon On Insulator Herstellung von hohlräumen in einer siliziumscheibe
FR2850487B1 (fr) * 2002-12-24 2005-12-09 Commissariat Energie Atomique Procede de realisation de substrats mixtes et structure ainsi obtenue
KR100546855B1 (ko) * 2002-12-28 2006-01-25 동부아남반도체 주식회사 반도체 소자의 제조 방법
JP4238724B2 (ja) * 2003-03-27 2009-03-18 株式会社デンソー 半導体装置
JP2004319538A (ja) * 2003-04-10 2004-11-11 Seiko Epson Corp 半導体装置の製造方法、集積回路、電子光学装置及び電子機器
US6936491B2 (en) * 2003-06-04 2005-08-30 Robert Bosch Gmbh Method of fabricating microelectromechanical systems and devices having trench isolated contacts
US6936522B2 (en) * 2003-06-26 2005-08-30 International Business Machines Corporation Selective silicon-on-insulator isolation structure and method
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

Also Published As

Publication number Publication date
KR20070046202A (ko) 2007-05-02
DE602005025375D1 (de) 2011-01-27
FR2875947B1 (fr) 2007-09-07
CN102637626A (zh) 2012-08-15
FR2875947A1 (fr) 2006-03-31
US20080036039A1 (en) 2008-02-14
JP2011098434A (ja) 2011-05-19
WO2006035031A1 (en) 2006-04-06
JP2008514441A (ja) 2008-05-08
CN101032014A (zh) 2007-09-05
EP1794789A1 (de) 2007-06-13
JP2011098435A (ja) 2011-05-19
US20130012024A1 (en) 2013-01-10
EP1794789B1 (de) 2010-12-15
KR100860546B1 (ko) 2008-09-26

Similar Documents

Publication Publication Date Title
DE602005025375D1 (de) Strukturen für mikroelektronik und mikrosystem sowie herstellungsverfahren
SG169394A1 (en) Method for producing partial soi structures comprising zones connecting a superficial layer and a substrate
DE502005008107D1 (de) Lichtdiffusor und verfahren zu dessen herstellung
ATE414673T1 (de) Schichtstruktur und herstellungsverfahren dafür
ATE532760T1 (de) Wabenstruktur und zugehöriges herstellungsverfahren
WO2003095358A3 (en) Method of forming manofluidic channels
ATE384819T1 (de) Method for making a polymeric garment material
BRPI0603696A (pt) elemento de mancal e processo para fabricação de um elemento de mancal
TW200628574A (en) Adhesion promoter, electroactive layer and electroactive device comprising same, and method
MY140142A (en) Method for manufacture of a multi-layer pipe
SE0502791L (sv) Metod för att uppta hål i värmesmältbara material
ATE552124T1 (de) Herstellungsverfahren für tafeln und dadurch gewonnene tafel
ATE500001T1 (de) Mikroreplizierter gegenstand und herstellungsverfahren dafür
DE112005000802A5 (de) Trennschichtträger
ATE471351T1 (de) Medizinische vorrichtungen und verfahren zu ihrer herstellung
WO2006138126A3 (en) Antistiction mems substrate and method of manufacture
TW200713420A (en) Method of fabricating shallow trench isolation structure
TW200704582A (en) Semiconductor composite device and method of manufacturing the same
ATE408486T1 (de) Holzwerkstoffplatte sowie ein verfahren zum herstellen einer holzwerkstoffplatte
ATE555325T1 (de) Riemen und markierverfahren
DE602006019452D1 (de) Verfahren zur Herstellung von mikrofluidischen Vorrichtungen und auf diese Weise hergestellte Vorrichtungen
ATE454807T1 (de) Verfahren zum herstellen eines leiterplattenelements sowie leiterplattenelement
TW200614427A (en) Semiconductor device having a smooth epi layer and a method for its manufacture
TW200630290A (en) Film peeling apparatus and method of manufacturing wiring board
ATE536263T1 (de) Verfahren zur plasmaverstärkten verbindung und durch plasmaverstärkte verbindung erzeugte verbundstrukturen

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties