AU636768B2 - Parallel data processing apparatus with signal skew compensation - Google Patents

Parallel data processing apparatus with signal skew compensation Download PDF

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Publication number
AU636768B2
AU636768B2 AU79273/91A AU7927391A AU636768B2 AU 636768 B2 AU636768 B2 AU 636768B2 AU 79273/91 A AU79273/91 A AU 79273/91A AU 7927391 A AU7927391 A AU 7927391A AU 636768 B2 AU636768 B2 AU 636768B2
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AU
Australia
Prior art keywords
signal
common
path
delay
pairs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU79273/91A
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English (en)
Other versions
AU7927391A (en
Inventor
Hiroki Iciki
Hideki Kato
Daiki Masumoto
Hideki Yoshizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
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Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of AU7927391A publication Critical patent/AU7927391A/en
Application granted granted Critical
Publication of AU636768B2 publication Critical patent/AU636768B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AU79273/91A 1990-06-28 1991-06-25 Parallel data processing apparatus with signal skew compensation Ceased AU636768B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2171069A JP2507677B2 (ja) 1990-06-28 1990-06-28 分散型デ―タ処理装置
JP2-171069 1990-06-28

Publications (2)

Publication Number Publication Date
AU7927391A AU7927391A (en) 1992-03-26
AU636768B2 true AU636768B2 (en) 1993-05-06

Family

ID=15916461

Family Applications (1)

Application Number Title Priority Date Filing Date
AU79273/91A Ceased AU636768B2 (en) 1990-06-28 1991-06-25 Parallel data processing apparatus with signal skew compensation

Country Status (6)

Country Link
US (1) US5220660A (fr)
EP (1) EP0464632B1 (fr)
JP (1) JP2507677B2 (fr)
AU (1) AU636768B2 (fr)
DE (1) DE69131822T2 (fr)
FI (1) FI913114A7 (fr)

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US5577214A (en) * 1992-05-18 1996-11-19 Opti, Inc. Programmable hold delay
US5572722A (en) * 1992-05-28 1996-11-05 Texas Instruments Incorporated Time skewing arrangement for operating random access memory in synchronism with a data processor
JPH0793386A (ja) * 1993-09-28 1995-04-07 Fujitsu Ltd Ｌｓｉ実装設計システム
US5467465A (en) * 1993-11-17 1995-11-14 Umax Data System Inc. Two clock method for synchronizing a plurality of identical processors connected in parallel
JPH07248847A (ja) * 1994-03-11 1995-09-26 Fujitsu Ltd クロック信号調整方法および装置
US5768620A (en) * 1996-04-09 1998-06-16 International Business Machines Corporation Variable timeout method in a missing-interrupt-handler for I/O requests issued by the same operating system
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US6557066B1 (en) 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
DE10006236C2 (de) * 2000-02-11 2001-12-20 Infineon Technologies Ag Anordnung zum Generieren von Signalimpulsen mit definierten Pulslängen in einem Baustein mit BIST-Funktion
JP3628265B2 (ja) * 2001-02-21 2005-03-09 株式会社半導体理工学研究センター マルチプロセッサシステム装置
KR100414943B1 (ko) * 2001-12-28 2004-01-16 엘지전자 주식회사 콤팩트 피씨아이에 기반한 다중 처리 시스템에서의 클럭분배 장치 및 방법
US7043649B2 (en) * 2002-11-20 2006-05-09 Portalplayer, Inc. System clock power management for chips with multiple processing modules
US7698490B2 (en) * 2005-12-21 2010-04-13 Nvidia Corporation Passive USB power configuration switching
US7414550B1 (en) 2006-06-30 2008-08-19 Nvidia Corporation Methods and systems for sample rate conversion and sample clock synchronization
US9209792B1 (en) 2007-08-15 2015-12-08 Nvidia Corporation Clock selection system and method
US9088176B2 (en) * 2007-12-17 2015-07-21 Nvidia Corporation Power management efficiency using DC-DC and linear regulators in conjunction
US8327173B2 (en) * 2007-12-17 2012-12-04 Nvidia Corporation Integrated circuit device core power down independent of peripheral device operation
US9411390B2 (en) 2008-02-11 2016-08-09 Nvidia Corporation Integrated circuit device having power domains and partitions based on use case power optimization
US9423846B2 (en) 2008-04-10 2016-08-23 Nvidia Corporation Powered ring to maintain IO state independent of the core of an integrated circuit device
US8762759B2 (en) * 2008-04-10 2014-06-24 Nvidia Corporation Responding to interrupts while in a reduced power state
JP5604799B2 (ja) * 2009-03-06 2014-10-15 日本電気株式会社 フォールトトレラントコンピュータ
JP5800752B2 (ja) * 2012-04-25 2015-10-28 三菱電機株式会社 信号源同期回路
US9395799B2 (en) 2012-08-09 2016-07-19 Nvidia Corporation Power management techniques for USB interfaces
US9471395B2 (en) 2012-08-23 2016-10-18 Nvidia Corporation Processor cluster migration techniques
US20140062561A1 (en) 2012-09-05 2014-03-06 Nvidia Corporation Schmitt receiver systems and methods for high-voltage input signals
EP2775655B1 (fr) * 2013-03-08 2020-10-28 Pro Design Electronic GmbH Procédé de distribution d'un signal d'horloge, système de distribution d'horloge et système électronique comprenant un système de distribution d'horloge

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU7529087A (en) * 1986-07-09 1988-01-14 Eta Systems Inc. Integrated circuit clock bus system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4063308A (en) * 1975-06-27 1977-12-13 International Business Machines Corporation Automatic clock tuning and measuring system for LSI computers
JPS63238714A (ja) * 1986-11-26 1988-10-04 Hitachi Ltd クロック供給システム
US4805196A (en) * 1987-04-29 1989-02-14 Gte Laboratories Incorporated Line delay compensation for digital transmission systems utilizing low power line drivers
US5086500A (en) * 1987-08-07 1992-02-04 Tektronix, Inc. Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
US5041966A (en) * 1987-10-06 1991-08-20 Nec Corporation Partially distributed method for clock synchronization
US4868522A (en) * 1988-12-13 1989-09-19 Gazelle Microcircuits, Inc. Clock signal distribution device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU7529087A (en) * 1986-07-09 1988-01-14 Eta Systems Inc. Integrated circuit clock bus system

Also Published As

Publication number Publication date
JP2507677B2 (ja) 1996-06-12
EP0464632A3 (en) 1993-08-25
DE69131822D1 (de) 2000-01-13
FI913114A7 (fi) 1991-12-29
JPH0460742A (ja) 1992-02-26
EP0464632B1 (fr) 1999-12-08
FI913114A0 (fi) 1991-06-26
US5220660A (en) 1993-06-15
EP0464632A2 (fr) 1992-01-08
DE69131822T2 (de) 2000-04-06
AU7927391A (en) 1992-03-26

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