CA2008749C - Tampon a rejection du bruit monte entre un ttl et l'entree d'un cmos - Google Patents

Tampon a rejection du bruit monte entre un ttl et l'entree d'un cmos

Info

Publication number
CA2008749C
CA2008749C CA002008749A CA2008749A CA2008749C CA 2008749 C CA2008749 C CA 2008749C CA 002008749 A CA002008749 A CA 002008749A CA 2008749 A CA2008749 A CA 2008749A CA 2008749 C CA2008749 C CA 2008749C
Authority
CA
Canada
Prior art keywords
output
inverter
buffer
input
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002008749A
Other languages
English (en)
Other versions
CA2008749A1 (fr
Inventor
Frank Wanlass
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Standard Microsystems LLC
Original Assignee
Standard Microsystems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Microsystems LLC filed Critical Standard Microsystems LLC
Publication of CA2008749A1 publication Critical patent/CA2008749A1/fr
Application granted granted Critical
Publication of CA2008749C publication Critical patent/CA2008749C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Networks Using Active Elements (AREA)
CA002008749A 1989-06-30 1990-01-29 Tampon a rejection du bruit monte entre un ttl et l'entree d'un cmos Expired - Fee Related CA2008749C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37520989A 1989-06-30 1989-06-30
US375,209 1989-06-30

Publications (2)

Publication Number Publication Date
CA2008749A1 CA2008749A1 (fr) 1990-12-31
CA2008749C true CA2008749C (fr) 1999-11-30

Family

ID=23479954

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002008749A Expired - Fee Related CA2008749C (fr) 1989-06-30 1990-01-29 Tampon a rejection du bruit monte entre un ttl et l'entree d'un cmos

Country Status (6)

Country Link
JP (1) JPH0342910A (fr)
CA (1) CA2008749C (fr)
DE (1) DE4004381A1 (fr)
FR (1) FR2649265B1 (fr)
GB (1) GB2233519B (fr)
IT (1) IT1238931B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930003929B1 (ko) * 1990-08-09 1993-05-15 삼성전자 주식회사 데이타 출력버퍼
KR920015363A (ko) * 1991-01-22 1992-08-26 김광호 Ttl 입력 버퍼회로
GB2258100B (en) * 1991-06-28 1995-02-15 Digital Equipment Corp Floating-well CMOS output driver
DE4127212A1 (de) * 1991-08-16 1993-02-18 Licentia Gmbh Schaltungsanordnung zur pegelumsetzung
JP2769653B2 (ja) * 1991-11-06 1998-06-25 三菱電機株式会社 反転回路
US6433983B1 (en) * 1999-11-24 2002-08-13 Honeywell Inc. High performance output buffer with ESD protection

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2046301A1 (de) * 1970-09-19 1972-04-20 Siemens Ag Herzüberwachungsgerät
US3769528A (en) * 1972-12-27 1973-10-30 Ibm Low power fet driver circuit
US3851189A (en) * 1973-06-25 1974-11-26 Hughes Aircraft Co Bisitable digital circuitry
NL8301711A (nl) * 1983-05-13 1984-12-03 Philips Nv Complementaire igfet schakeling.
EP0209805B1 (fr) * 1985-07-22 1993-04-07 Hitachi, Ltd. Dispositif à semi-conducteurs à transistor bipolaire et transistor à effet de champ à grille isolée
US4740717A (en) * 1986-11-25 1988-04-26 North American Philips Corporation, Signetics Division Switching device with dynamic hysteresis
US4859873A (en) * 1987-07-17 1989-08-22 Western Digital Corporation CMOS Schmitt trigger with independently biased high/low threshold circuits

Also Published As

Publication number Publication date
IT9009396A0 (it) 1990-05-21
CA2008749A1 (fr) 1990-12-31
IT9009396A1 (it) 1991-01-01
FR2649265B1 (fr) 1993-12-17
DE4004381A1 (de) 1991-01-03
GB2233519B (en) 1994-07-06
JPH0342910A (ja) 1991-02-25
FR2649265A1 (fr) 1991-01-04
GB9014597D0 (en) 1990-08-22
IT1238931B (it) 1993-09-07
GB2233519A (en) 1991-01-09

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed