JPH0342910A - バッファ回路 - Google Patents

バッファ回路

Info

Publication number
JPH0342910A
JPH0342910A JP2166940A JP16694090A JPH0342910A JP H0342910 A JPH0342910 A JP H0342910A JP 2166940 A JP2166940 A JP 2166940A JP 16694090 A JP16694090 A JP 16694090A JP H0342910 A JPH0342910 A JP H0342910A
Authority
JP
Japan
Prior art keywords
inverter
output
buffer circuit
transistor
charging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2166940A
Other languages
English (en)
Japanese (ja)
Inventor
Frank Wanlass
フランク ワンラス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SMC STANDARD MICROSYST CORP
Standard Microsystems LLC
Original Assignee
SMC STANDARD MICROSYST CORP
Standard Microsystems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SMC STANDARD MICROSYST CORP, Standard Microsystems LLC filed Critical SMC STANDARD MICROSYST CORP
Publication of JPH0342910A publication Critical patent/JPH0342910A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/3565Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Networks Using Active Elements (AREA)
JP2166940A 1989-06-30 1990-06-27 バッファ回路 Pending JPH0342910A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37520989A 1989-06-30 1989-06-30
US375209 1989-06-30

Publications (1)

Publication Number Publication Date
JPH0342910A true JPH0342910A (ja) 1991-02-25

Family

ID=23479954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2166940A Pending JPH0342910A (ja) 1989-06-30 1990-06-27 バッファ回路

Country Status (6)

Country Link
JP (1) JPH0342910A (fr)
CA (1) CA2008749C (fr)
DE (1) DE4004381A1 (fr)
FR (1) FR2649265B1 (fr)
GB (1) GB2233519B (fr)
IT (1) IT1238931B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930003929B1 (ko) * 1990-08-09 1993-05-15 삼성전자 주식회사 데이타 출력버퍼
KR920015363A (ko) * 1991-01-22 1992-08-26 김광호 Ttl 입력 버퍼회로
GB2258100B (en) * 1991-06-28 1995-02-15 Digital Equipment Corp Floating-well CMOS output driver
DE4127212A1 (de) * 1991-08-16 1993-02-18 Licentia Gmbh Schaltungsanordnung zur pegelumsetzung
JP2769653B2 (ja) * 1991-11-06 1998-06-25 三菱電機株式会社 反転回路
US6433983B1 (en) * 1999-11-24 2002-08-13 Honeywell Inc. High performance output buffer with ESD protection

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2046301A1 (de) * 1970-09-19 1972-04-20 Siemens Ag Herzüberwachungsgerät
US3769528A (en) * 1972-12-27 1973-10-30 Ibm Low power fet driver circuit
US3851189A (en) * 1973-06-25 1974-11-26 Hughes Aircraft Co Bisitable digital circuitry
NL8301711A (nl) * 1983-05-13 1984-12-03 Philips Nv Complementaire igfet schakeling.
EP0209805B1 (fr) * 1985-07-22 1993-04-07 Hitachi, Ltd. Dispositif à semi-conducteurs à transistor bipolaire et transistor à effet de champ à grille isolée
US4740717A (en) * 1986-11-25 1988-04-26 North American Philips Corporation, Signetics Division Switching device with dynamic hysteresis
US4859873A (en) * 1987-07-17 1989-08-22 Western Digital Corporation CMOS Schmitt trigger with independently biased high/low threshold circuits

Also Published As

Publication number Publication date
IT9009396A0 (it) 1990-05-21
CA2008749A1 (fr) 1990-12-31
IT9009396A1 (it) 1991-01-01
CA2008749C (fr) 1999-11-30
FR2649265B1 (fr) 1993-12-17
DE4004381A1 (de) 1991-01-03
GB2233519B (en) 1994-07-06
FR2649265A1 (fr) 1991-01-04
GB9014597D0 (en) 1990-08-22
IT1238931B (it) 1993-09-07
GB2233519A (en) 1991-01-09

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