CA2032073A1 - Methode de fabrication a deux cuves - Google Patents

Methode de fabrication a deux cuves

Info

Publication number
CA2032073A1
CA2032073A1 CA002032073A CA2032073A CA2032073A1 CA 2032073 A1 CA2032073 A1 CA 2032073A1 CA 002032073 A CA002032073 A CA 002032073A CA 2032073 A CA2032073 A CA 2032073A CA 2032073 A1 CA2032073 A1 CA 2032073A1
Authority
CA
Canada
Prior art keywords
substrate
conductivity type
impurity
implanting
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002032073A
Other languages
English (en)
Inventor
Pierre Huet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor ULC
Original Assignee
Mitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corp filed Critical Mitel Corp
Priority to CA002032073A priority Critical patent/CA2032073A1/fr
Priority to EP92900803A priority patent/EP0561909A1/fr
Priority to KR1019930701761A priority patent/KR930703698A/ko
Priority to PCT/CA1991/000441 priority patent/WO1992010851A1/fr
Priority to JP4501624A priority patent/JPH06503445A/ja
Publication of CA2032073A1 publication Critical patent/CA2032073A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Element Separation (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Thermistors And Varistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CA002032073A 1990-12-12 1990-12-12 Methode de fabrication a deux cuves Abandoned CA2032073A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CA002032073A CA2032073A1 (fr) 1990-12-12 1990-12-12 Methode de fabrication a deux cuves
EP92900803A EP0561909A1 (fr) 1990-12-12 1991-12-11 Procede de fabrication de caissons jumeles
KR1019930701761A KR930703698A (ko) 1990-12-12 1991-12-11 터브쌍 제조 방법
PCT/CA1991/000441 WO1992010851A1 (fr) 1990-12-12 1991-12-11 Procede de fabrication de caissons jumeles
JP4501624A JPH06503445A (ja) 1990-12-12 1991-12-11 ツインタブ形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002032073A CA2032073A1 (fr) 1990-12-12 1990-12-12 Methode de fabrication a deux cuves

Publications (1)

Publication Number Publication Date
CA2032073A1 true CA2032073A1 (fr) 1992-06-13

Family

ID=4146636

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002032073A Abandoned CA2032073A1 (fr) 1990-12-12 1990-12-12 Methode de fabrication a deux cuves

Country Status (5)

Country Link
EP (1) EP0561909A1 (fr)
JP (1) JPH06503445A (fr)
KR (1) KR930703698A (fr)
CA (1) CA2032073A1 (fr)
WO (1) WO1992010851A1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
DE3330851A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4558508A (en) * 1984-10-15 1985-12-17 International Business Machines Corporation Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step
JPS6197859A (ja) * 1984-10-18 1986-05-16 Matsushita Electronics Corp 相補型ｍｏｓ集積回路の製造方法

Also Published As

Publication number Publication date
JPH06503445A (ja) 1994-04-14
KR930703698A (ko) 1993-11-30
WO1992010851A1 (fr) 1992-06-25
EP0561909A1 (fr) 1993-09-29

Similar Documents

Publication Publication Date Title
US4269636A (en) Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
US4272880A (en) MOS/SOS Process
US4554726A (en) CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4575925A (en) Method for fabricating a SOI type semiconductor device
US4697332A (en) Method of making tri-well CMOS by self-aligned process
JPH05347383A (ja) 集積回路の製法
JPH0754825B2 (ja) 部分的誘電体分離半導体装置
JPH0697665B2 (ja) 集積回路構成体の製造方法
KR970018527A (ko) 반도체 장치 및 그 제조 방법
KR100189739B1 (ko) 반도체 기판에 삼중웰을 형성하는 방법
US3933528A (en) Process for fabricating integrated circuits utilizing ion implantation
EP0386798A2 (fr) Procédé de fabrication de régions d'interruption de canal dans une structure semi-conductrice
GB2111305A (en) Method of forming ion implanted regions self-aligned with overlying insulating layer portions
US4535529A (en) Method of making semiconductor devices by forming an impurity adjusted epitaxial layer over out diffused buried layers having different lateral conductivity types
US6403447B1 (en) Reduced substrate capacitance high performance SOI process
US4034395A (en) Monolithic integrated circuit having a plurality of resistor regions electrically connected in series
US4622738A (en) Method of making integrated bipolar semiconductor device by first forming junction isolation regions and recessed oxide isolation regions without birds beak
US5525823A (en) Manufacture of CMOS devices
US6645854B1 (en) Formation of a vertical junction throuph process simulation based optimization of implant doses and energies
CA2032073A1 (fr) Methode de fabrication a deux cuves
US4092662A (en) Sensistor apparatus
EP0656652B1 (fr) Procédé pour former des régions d'isolations dans des circuits intégrés
EP0182876B1 (fr) Technologie cmos a puits de trois types
US5179030A (en) Method of fabricating a buried zener diode simultaneously with other semiconductor devices
EP0111097B1 (fr) Procédé pour fabriquer des dispositifs à semi-conducteur ayant un diélectrique de champ épais et un interrupteur de canal autoaligné

Legal Events

Date Code Title Description
FZDE Discontinued