CN1198252A - 用于集成电路的含有用专用腔室淀积的两薄层钛的金属堆栈 - Google Patents

用于集成电路的含有用专用腔室淀积的两薄层钛的金属堆栈 Download PDF

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Publication number
CN1198252A
CN1198252A CN96197259A CN96197259A CN1198252A CN 1198252 A CN1198252 A CN 1198252A CN 96197259 A CN96197259 A CN 96197259A CN 96197259 A CN96197259 A CN 96197259A CN 1198252 A CN1198252 A CN 1198252A
Authority
CN
China
Prior art keywords
titanium
layer
metal stack
deck
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN96197259A
Other languages
English (en)
Chinese (zh)
Inventor
R·拉斯托吉
白鹏
S·阿梅德
W·K·梅耶尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1198252A publication Critical patent/CN1198252A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
CN96197259A 1995-09-29 1996-09-25 用于集成电路的含有用专用腔室淀积的两薄层钛的金属堆栈 Pending CN1198252A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53615595A 1995-09-29 1995-09-29
US08/536,155 1995-09-29

Publications (1)

Publication Number Publication Date
CN1198252A true CN1198252A (zh) 1998-11-04

Family

ID=24137384

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96197259A Pending CN1198252A (zh) 1995-09-29 1996-09-25 用于集成电路的含有用专用腔室淀积的两薄层钛的金属堆栈

Country Status (7)

Country Link
EP (1) EP0852809A4 (de)
JP (1) JPH11511593A (de)
KR (1) KR19990063767A (de)
CN (1) CN1198252A (de)
AU (1) AU7245396A (de)
IL (1) IL123751A0 (de)
WO (1) WO1997012399A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316613C (zh) * 2003-06-19 2007-05-16 旺宏电子股份有限公司 半导体的三明治抗反射结构金属层及其制程
CN1324675C (zh) * 2003-04-02 2007-07-04 旺宏电子股份有限公司 防止微影工艺对准失误的结构与方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19903195B4 (de) 1999-01-27 2005-05-19 Infineon Technologies Ag Verfahren zur Verbesserung der Qualität von Metalleitbahnen auf Halbleiterstrukturen
US6492281B1 (en) * 2000-09-22 2002-12-10 Advanced Micro Devices, Inc. Method of fabricating conductor structures with metal comb bridging avoidance
DE10053915C2 (de) * 2000-10-31 2002-11-14 Infineon Technologies Ag Herstellungsverfahren für eine integrierte Schaltung
KR100650904B1 (ko) * 2005-12-29 2006-11-28 동부일렉트로닉스 주식회사 알루미늄 배선 형성 방법
KR102036942B1 (ko) 2012-02-24 2019-10-25 스카이워크스 솔루션즈, 인코포레이티드 화합물 반도체용 구리 상호접속부에 관련된 개선된 구조체, 소자 및 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673623A (en) * 1985-05-06 1987-06-16 The Board Of Trustees Of The Leland Stanford Junior University Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects
US5231053A (en) * 1990-12-27 1993-07-27 Intel Corporation Process of forming a tri-layer titanium coating for an aluminum layer of a semiconductor device
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5470790A (en) * 1994-10-17 1995-11-28 Intel Corporation Via hole profile and method of fabrication
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
US5747879A (en) * 1995-09-29 1998-05-05 Intel Corporation Interface between titanium and aluminum-alloy in metal stack for integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1324675C (zh) * 2003-04-02 2007-07-04 旺宏电子股份有限公司 防止微影工艺对准失误的结构与方法
CN1316613C (zh) * 2003-06-19 2007-05-16 旺宏电子股份有限公司 半导体的三明治抗反射结构金属层及其制程

Also Published As

Publication number Publication date
EP0852809A1 (de) 1998-07-15
IL123751A0 (en) 1998-10-30
AU7245396A (en) 1997-04-17
EP0852809A4 (de) 1999-09-15
WO1997012399A1 (en) 1997-04-03
JPH11511593A (ja) 1999-10-05
KR19990063767A (ko) 1999-07-26

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