JPH11511593A - 専用チャンバによる２層のチタン薄層を有する集積回路用金属スタック - Google Patents

専用チャンバによる２層のチタン薄層を有する集積回路用金属スタック

Info

Publication number
JPH11511593A
JPH11511593A JP9512195A JP51219597A JPH11511593A JP H11511593 A JPH11511593 A JP H11511593A JP 9512195 A JP9512195 A JP 9512195A JP 51219597 A JP51219597 A JP 51219597A JP H11511593 A JPH11511593 A JP H11511593A
Authority
JP
Japan
Prior art keywords
layer
titanium
metal stack
stack
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9512195A
Other languages
English (en)
Japanese (ja)
Inventor
ラストギ，ラジヴ
バイ，ペン
アーメッド，ソヘイル
メイヤー，ウイリアム・ケイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JPH11511593A publication Critical patent/JPH11511593A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP9512195A 1995-09-29 1996-09-25 専用チャンバによる２層のチタン薄層を有する集積回路用金属スタック Pending JPH11511593A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US53615595A 1995-09-29 1995-09-29
US08/536,155 1995-09-29
PCT/US1996/015351 WO1997012399A1 (en) 1995-09-29 1996-09-25 Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions

Publications (1)

Publication Number Publication Date
JPH11511593A true JPH11511593A (ja) 1999-10-05

Family

ID=24137384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9512195A Pending JPH11511593A (ja) 1995-09-29 1996-09-25 専用チャンバによる２層のチタン薄層を有する集積回路用金属スタック

Country Status (7)

Country Link
EP (1) EP0852809A4 (de)
JP (1) JPH11511593A (de)
KR (1) KR19990063767A (de)
CN (1) CN1198252A (de)
AU (1) AU7245396A (de)
IL (1) IL123751A0 (de)
WO (1) WO1997012399A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19903195B4 (de) 1999-01-27 2005-05-19 Infineon Technologies Ag Verfahren zur Verbesserung der Qualität von Metalleitbahnen auf Halbleiterstrukturen
US6492281B1 (en) * 2000-09-22 2002-12-10 Advanced Micro Devices, Inc. Method of fabricating conductor structures with metal comb bridging avoidance
DE10053915C2 (de) * 2000-10-31 2002-11-14 Infineon Technologies Ag Herstellungsverfahren für eine integrierte Schaltung
CN1324675C (zh) * 2003-04-02 2007-07-04 旺宏电子股份有限公司 防止微影工艺对准失误的结构与方法
CN1316613C (zh) * 2003-06-19 2007-05-16 旺宏电子股份有限公司 半导体的三明治抗反射结构金属层及其制程
KR100650904B1 (ko) * 2005-12-29 2006-11-28 동부일렉트로닉스 주식회사 알루미늄 배선 형성 방법
CN104221130B (zh) 2012-02-24 2018-04-24 天工方案公司 与化合物半导体的铜互连相关的改善的结构、装置和方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673623A (en) * 1985-05-06 1987-06-16 The Board Of Trustees Of The Leland Stanford Junior University Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects
US5231053A (en) * 1990-12-27 1993-07-27 Intel Corporation Process of forming a tri-layer titanium coating for an aluminum layer of a semiconductor device
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5470790A (en) * 1994-10-17 1995-11-28 Intel Corporation Via hole profile and method of fabrication
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
US5747879A (en) * 1995-09-29 1998-05-05 Intel Corporation Interface between titanium and aluminum-alloy in metal stack for integrated circuit

Also Published As

Publication number Publication date
KR19990063767A (ko) 1999-07-26
EP0852809A1 (de) 1998-07-15
CN1198252A (zh) 1998-11-04
WO1997012399A1 (en) 1997-04-03
AU7245396A (en) 1997-04-17
EP0852809A4 (de) 1999-09-15
IL123751A0 (en) 1998-10-30

Similar Documents

Publication Publication Date Title
EP0721216B1 (de) Weicher Metallleiter und Herstellungsverfahren
US6255733B1 (en) Metal-alloy interconnections for integrated circuits
US5565707A (en) Interconnect structure using a Al2 Cu for an integrated circuit chip
JP3053718B2 (ja) 集積回路構造に対し重ねてパターン形成された金属層に電気的に接続されているビアにおける低抵抗アルミニウムプラグの形成方法
US7417321B2 (en) Via structure and process for forming the same
EP1570517B1 (de) Ein verfahren zur abscheidung einer metallschicht auf einer halbleiter-interkonnektstruktur mit einer deckschicht
WO2004053926A2 (en) A method for depositing a metal layer on a semiconductor interconnect structure
US5747879A (en) Interface between titanium and aluminum-alloy in metal stack for integrated circuit
US6054382A (en) Method of improving texture of metal films in semiconductor integrated circuits
US5976970A (en) Method of making and laterally filling key hole structure for ultra fine pitch conductor lines
WO2001029892A1 (en) Self-aligned metal caps for interlevel metal connections
US6372645B1 (en) Methods to reduce metal bridges and line shorts in integrated circuits
JP2002033323A (ja) 銅相互接続部を有する半導体デバイスの製造方法
JPH11511593A (ja) 専用チャンバによる２層のチタン薄層を有する集積回路用金属スタック
US6876082B2 (en) Refractory metal nitride barrier layer with gradient nitrogen concentration
JP2770945B2 (ja) タングステン被覆法
TWI269403B (en) Sacrificial metal liner for copper
US6200894B1 (en) Method for enhancing aluminum interconnect properties
US7943505B2 (en) Advanced VLSI metallization
EP0877424A2 (de) Verbindungsmethode und Struktur für Halbleiterschaltungen
JPH10106972A (ja) 電極配線構造の製造方法
KR100286253B1 (ko) 질소플라즈마를 이용한 선택적 금속박막 증착방법 및 그를 이용한 다층금속 연결배선 방법
US20050064705A1 (en) Method for producing thin metal-containing layers having a low electrical resistance
JP2001035850A (ja) 半導体装置及びその製造方法
JP2002141303A (ja) 向上した濡れ性、障壁効率、デバイス信頼性を有する拡散障壁材料におけるＳｉの現場同時堆積