EP0000545A1 - Procédé de fabrication d'un dispositif semiconducteur à auto-alignement - Google Patents

Procédé de fabrication d'un dispositif semiconducteur à auto-alignement Download PDF

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Publication number
EP0000545A1
EP0000545A1 EP78100443A EP78100443A EP0000545A1 EP 0000545 A1 EP0000545 A1 EP 0000545A1 EP 78100443 A EP78100443 A EP 78100443A EP 78100443 A EP78100443 A EP 78100443A EP 0000545 A1 EP0000545 A1 EP 0000545A1
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EP
European Patent Office
Prior art keywords
layer
semiconductor
semiconductor body
regions
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP78100443A
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German (de)
English (en)
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EP0000545B1 (fr
Inventor
Chakrapani Gajanan Jambotkar
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials

Definitions

  • the invention relates to a method for producing a semiconductor arrangement of the type specified in the preamble of claim 1.
  • a preferred field of application of this method is the production of insulating layer field-effect transistor structures which are equipped with so-called self-aligned gate electrodes.
  • Such field effect transistors with a self-aligned gate are already known per se.
  • the associated conventional manufacturing methods use a mask made of a high temperature-resistant material, ie a material that is able to withstand high temperatures in the order of magnitude of 1000 ° C. and higher, for masking during the formation of the source and drain regions.
  • This masking layer may, for example, be made of silicon, as described for the processes described in US Pat. Nos. 3,475,234 and 3,544,399, using polycrystalline silicon as the masking material which remains in the gate area for the final formation of the gate electrode. Since such structures are insulated-layer field-effect transistors, is still a layer of an insulating material, e.g. B. from silicon dioxide, be present under the silicon-containing masking layer.
  • the high temperature resistant material itself can already be an insulating material, e.g. B. silicon nitride, which remains as a gate dielectric in the gate region.
  • the high temperature resistant material z. B. silicon nitride or a double layer of silicon nitride over silicon dioxide, for edge definition of the source and drain regions adjacent to the gate region; it remains as a thin gate dielectric in the final field effect transistor structure.
  • a thick oxide layer is thermally grown over the source and drain, the silicon nitride layer present in the gate region serving as an oxidation-inhibiting mask to prevent the thickness of the thin gate insulating layer from increasing.
  • a conductive gate electrode is formed in the gate area, the thin silicon nitride layer or, after its removal, another thin insulating layer also serving to delimit the area provided as the gate area.
  • the dopants can first be introduced by diffusion or ion implantation in such a way that very flat surface areas of the appropriate conductivity type form, which is followed by a so-called driving-in step to be carried out at high temperatures, through which the source and drain are driven deeper into the semiconductor body.
  • driving-in step to be carried out at high temperatures, through which the source and drain are driven deeper into the semiconductor body.
  • the doping atoms migrate to a certain extent below the gate masking layer. As a result, there was nevertheless an overlap of the gate with the source and drain and the resulting disadvantageous consequences.
  • the invention achieves the object of specifying a method for producing a semiconductor arrangement, in particular an insulating layer field-effect transistor structure, which is improved with respect to the overlap-free self-adjustment of doping regions relative to a surface layer, in which the overlap-free self-adjustment also occurs at relatively deep in doping regions reaching the semiconductor body can be achieved.
  • buried areas completely enclosed by the material of the semiconductor body are first formed in the mutual arrangement defined by the masking layer on the semiconductor surface by means of ion implantation, whereupon a subsequent heat treatment brings about a targeted expansion of the dopants present in the buried areas until the semiconductor surface is reached.
  • the channel region is always exactly and completely covered by the gate electrode, but on the other hand that there is no gate overlap with the source and drain regions formed in this way.
  • FIG. 1 shows a semiconductor body or a substrate 10 of the P conductivity type, the specific resistance value of which is approximately 0.1 to 10 cm and on which an approximately 900 nm thick silicon dioxide layer 11 is formed.
  • This layer 11 can be produced in a conventional manner by thermal oxidation or deposited in another way, e.g. B. by vapor deposition or sputtering.
  • An opening 12 is produced in the layer 11 using conventional photolithography and etching methods, so that the structure shown in FIG. 1 results.
  • a thin layer 13 of silicon dioxide with a thickness of approximately 50 nm is then allowed to grow in the area of the opening 12, preferably thermally.
  • a silicon layer 14 is applied over this by means of conventional methods for depositing silicon, for example described in US Pat. No. 3,424,629. This process step is carried out at a temperature on the order of 500 to 900 ° C and usually at atmospheric pressure.
  • the silicon layer 14 is a polycrystalline structure since it is based on the Silicon dioxide layers 11 and 13 is formed.
  • the thickness of the layer 14 is approximately 900 nm.
  • an approximately 80 nm thick silicon dioxide layer 15 is produced in a conventional manner per se, but preferably by thermal oxidation of a part of the surface of the silicon layer 14.
  • the regions 18 and 19 buried in the semiconductor body 10 are then formed by means of ion implantation in accordance with FIG. 4.
  • N-type dopants e.g. B. phosphorus
  • the implantation step can be carried out either directly through the unmasked, relatively thin silicon dioxide layer 13 or, as shown in FIG. 4, after the silicon dioxide layer 13 not covered by the silicon layer 14 'has been removed beforehand.
  • the one below the mask is in the form of silicon layer 14 'arranged silicon dioxide layer designated 13'.
  • a conventional etching process e.g. B. can be used using a buffered hydrofluoric acid.
  • the silicon dioxide layer 15 will also be removed, while the layer 11, which is considerably thicker in comparison, remains essentially unchanged.
  • the ion implantation must be carried out with sufficient beam dosing and energy that the concentration distribution for the buried regions 18 and 19 results in the following aspects.
  • the same heat treatment is intended to ensure that regions 18 and 19 also move upwards expand in the direction of the surface of the semiconductor body 10 so that they just adjoin the silicon gate electrode laterally on the semiconductor surface.
  • FIG. 8A shows the concentration distribution of the N-doping impurities for the regions 18 and 19 along the section line 8A-8A shown in FIG. 4.
  • the regions 18 and 19 are originally regions which are completely enclosed in the P-conducting semiconductor body 10 generated, with a peak concentration at about 0.5 pm from the semiconductor surface.
  • the implantation step that can be used to form these areas 18 and 19 with the concentration profile shown can be carried out using conventional devices and methods, such as are described, for example, in US Pat. No. 3,756,862. For example, taking 31p + ions, an energy value of 400 keV and a dosage of approximately 10 16 ions / cm 2 is appropriate.
  • the implantation also forms a dopant distribution similar to the shape shown in FIG. 8A in the silicon layer region 14 ′. As a result, the layer 14 'is desirably provided with a low sheet resistance.
  • a so-called diffusion or driving-in step is carried out at a temperature of approximately 950 ° C. in a conventional oxidizing atmosphere, such as, for example, B. steam, performed to bring the source and drain regions 18 and 19 into the form shown in FIG. 5.
  • a conventional oxidizing atmosphere such as, for example, B. steam
  • the final dopant distribution for the source and drain regions 18 and 19 along the section line 8B-8B shown in FIG. 5 is shown in FIG. 8B.
  • a silicon dioxide layer 40 is formed over the semiconductor body 10 as well as over the polycrystalline silicon gate electrode 14 '.
  • the source and drain region edges next to it due to the subsequent diffusion or heat treatment step their downward expansion to the same extent can also be extended upward so that their intersections 22 and 23 (in FIG. 5) are practically exactly aligned with the corresponding edges 24 and 25 of the silicon gate electrode 14 'with regard to their lateral adjustment.
  • the preliminary ion implantation step according to FIG. 8A has such a distribution that, following the diffusion or heat treatment, the final impurity concentration on the surface of regions 18 and 19 (point 26 in FIG. 8B) is somewhat higher than the basic doping (point 27 8B) of the silicon semiconductor body 10.
  • openings 31, 32 and 28 are then produced in the silicon dioxide layer 40 as contact openings for source, drain and the gate electrode.
  • the source and drain regions have a relatively low surface concentration of phosphorus. It is therefore advantageous to in each case in these contact openings a flat implantation of the dopants causing N-type conduction, z.
  • the areas designated in Fig. 6 with 29, 30 and 34 be formed. These areas have a high surface concentration of the N conductivity type in the order of 10 21 atoms / cm 3, cf. in addition the concentration profile shown in FIG. 8C for the relationships shown in FIG. 6, and in particular the point 33 in FIG. 8C.
  • N + conductive connection regions 29, 30 and 34 can be produced in a conventional manner by introducing dopants. However, it is preferable to implant these areas by implanting N-type ions, e.g. B. phosphorus, using the method described above with an energy of about 40 keV and a dosage of about 10 16 ions / cm 2 . 7, the contact and connection metallization in the form of the connections 35, 36 and 37 for the source, drain and the silicon gate is formed in a conventional manner. This metallization can be completely conventional in the usual way with such integrated FET circuits, e.g. B. made of aluminum.
  • N-type ions e.g. B. phosphorus
  • the invention is not restricted to this but can also be applied to other self-aligned gate designs.
  • the masking layer required to ensure the self-alignment of the thin gate insulating layer consists of a material which does not melt or decompose in any other way at the diffusion temperatures of the order of 1000 ° C. or greater that are used.
  • Such other possibilities include, for example, self-aligned field effect transistors with a silicon nitride gate technology, in which a thin layer made of silicon nitride for self-aligning formation of the source and drain regions relative to the thin gate insulating layer.
  • high-temperature-resistant metals, eg. B. use molybdenum, tungsten or tantalum instead of the silicon described in the present embodiment.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
EP78100443A 1977-08-01 1978-07-19 Procédé de fabrication d'un dispositif semiconducteur à auto-alignement Expired EP0000545B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US820991 1977-08-01
US05/820,991 US4128439A (en) 1977-08-01 1977-08-01 Method for forming self-aligned field effect device by ion implantation and outdiffusion

Publications (2)

Publication Number Publication Date
EP0000545A1 true EP0000545A1 (fr) 1979-02-07
EP0000545B1 EP0000545B1 (fr) 1981-02-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100443A Expired EP0000545B1 (fr) 1977-08-01 1978-07-19 Procédé de fabrication d'un dispositif semiconducteur à auto-alignement

Country Status (6)

Country Link
US (1) US4128439A (fr)
EP (1) EP0000545B1 (fr)
JP (1) JPS6046831B2 (fr)
CA (1) CA1112374A (fr)
DE (1) DE2860467D1 (fr)
IT (1) IT1108994B (fr)

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US4218267A (en) * 1979-04-23 1980-08-19 Rockwell International Corporation Microelectronic fabrication method minimizing threshold voltage variation
JPS55151349A (en) * 1979-05-15 1980-11-25 Matsushita Electronics Corp Forming method of insulation isolating region
US4338616A (en) * 1980-02-19 1982-07-06 Xerox Corporation Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain
US4391651A (en) * 1981-10-15 1983-07-05 The United States Of America As Represented By The Secretary Of The Navy Method of forming a hyperabrupt interface in a GaAs substrate
JPS58170067A (ja) * 1982-03-31 1983-10-06 Fujitsu Ltd 薄膜トランジスタの製造方法
NL188923C (nl) * 1983-07-05 1992-11-02 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4648175A (en) * 1985-06-12 1987-03-10 Ncr Corporation Use of selectively deposited tungsten for contact formation and shunting metallization
US4734752A (en) * 1985-09-27 1988-03-29 Advanced Micro Devices, Inc. Electrostatic discharge protection device for CMOS integrated circuit outputs
EP0248988B1 (fr) * 1986-06-10 1990-10-31 Siemens Aktiengesellschaft Procédé pour fabriquer des circuits à transistors complémentaires à effet de champ du type MOS à haute intégration
US5602403A (en) * 1991-03-01 1997-02-11 The United States Of America As Represented By The Secretary Of The Navy Ion Implantation buried gate insulator field effect transistor
JPH05283710A (ja) * 1991-12-06 1993-10-29 Intel Corp 高電圧ｍｏｓトランジスタ及びその製造方法
KR0166101B1 (ko) * 1993-10-21 1999-01-15 김주용 정전방전 보호회로의 트랜지스터 및 그 제조방법
JPH0955496A (ja) * 1995-08-17 1997-02-25 Oki Electric Ind Co Ltd 高耐圧ｍｏｓトランジスタ及びその製造方法
EP1050562A1 (fr) * 1999-05-04 2000-11-08 Fina Research S.A. Composition à faible teneur en aromatiques
KR100640207B1 (ko) * 1999-10-29 2006-10-31 엘지.필립스 엘시디 주식회사 박막트랜지스터 및 그 제조방법

Citations (5)

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Publication number Priority date Publication date Assignee Title
GB1348066A (en) * 1970-05-13 1974-03-13 Hitachi Ltd Metal insulation semiconductor field effect transistors
US3936857A (en) * 1973-07-02 1976-02-03 Nippon Electric Company Limited Insulated gate field effect transistor having high transconductance
US4029522A (en) * 1976-06-30 1977-06-14 International Business Machines Corporation Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors
FR2334198A1 (fr) * 1975-12-03 1977-07-01 Siemens Ag Procede d'obtention d'une amplification en courant inverse localement elevee dans un transistor planar
DE2726003A1 (de) * 1976-06-23 1977-12-29 Hitachi Ltd Verfahren zur herstellung von mis- bauelementen mit versetztem gate

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US3449643A (en) * 1966-09-09 1969-06-10 Hitachi Ltd Semiconductor integrated circuit device
BE758683A (fr) * 1969-11-10 1971-05-10 Ibm Procede de fabrication d'un dispositif monolithique auto-isolant et structure de transistor a socle
US3734787A (en) * 1970-01-09 1973-05-22 Ibm Fabrication of diffused junction capacitor by simultaneous outdiffusion
US4058887A (en) * 1971-02-19 1977-11-22 Ibm Corporation Method for forming a transistor comprising layers of silicon dioxide and silicon nitride
US4032372A (en) * 1971-04-28 1977-06-28 International Business Machines Corporation Epitaxial outdiffusion technique for integrated bipolar and field effect transistors
FR2257998B1 (fr) * 1974-01-10 1976-11-26 Commissariat Energie Atomique
US3899373A (en) * 1974-05-20 1975-08-12 Ibm Method for forming a field effect device
US4001048A (en) * 1974-06-26 1977-01-04 Signetics Corporation Method of making metal oxide semiconductor structures using ion implantation
US3948694A (en) * 1975-04-30 1976-04-06 Motorola, Inc. Self-aligned method for integrated circuit manufacture
US4046606A (en) * 1976-05-10 1977-09-06 Rca Corporation Simultaneous location of areas having different conductivities
JPS52135685A (en) * 1976-05-10 1977-11-12 Nec Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1348066A (en) * 1970-05-13 1974-03-13 Hitachi Ltd Metal insulation semiconductor field effect transistors
US3936857A (en) * 1973-07-02 1976-02-03 Nippon Electric Company Limited Insulated gate field effect transistor having high transconductance
FR2334198A1 (fr) * 1975-12-03 1977-07-01 Siemens Ag Procede d'obtention d'une amplification en courant inverse localement elevee dans un transistor planar
DE2726003A1 (de) * 1976-06-23 1977-12-29 Hitachi Ltd Verfahren zur herstellung von mis- bauelementen mit versetztem gate
US4029522A (en) * 1976-06-30 1977-06-14 International Business Machines Corporation Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors

Also Published As

Publication number Publication date
JPS5427376A (en) 1979-03-01
CA1112374A (fr) 1981-11-10
IT7826098A0 (it) 1978-07-26
JPS6046831B2 (ja) 1985-10-18
US4128439A (en) 1978-12-05
IT1108994B (it) 1985-12-16
EP0000545B1 (fr) 1981-02-11
DE2860467D1 (en) 1981-03-26

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