EP1439576A3 - Verfahren zur Herstellung eines Durchgangsloches - Google Patents

Verfahren zur Herstellung eines Durchgangsloches Download PDF

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Publication number
EP1439576A3
EP1439576A3 EP04250045A EP04250045A EP1439576A3 EP 1439576 A3 EP1439576 A3 EP 1439576A3 EP 04250045 A EP04250045 A EP 04250045A EP 04250045 A EP04250045 A EP 04250045A EP 1439576 A3 EP1439576 A3 EP 1439576A3
Authority
EP
European Patent Office
Prior art keywords
metal film
forming
hole
bump
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP04250045A
Other languages
English (en)
French (fr)
Other versions
EP1439576A2 (de
EP1439576B1 (de
Inventor
Kei Shinko Electric Industries Co Ltd Murayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Publication of EP1439576A2 publication Critical patent/EP1439576A2/de
Publication of EP1439576A3 publication Critical patent/EP1439576A3/de
Application granted granted Critical
Publication of EP1439576B1 publication Critical patent/EP1439576B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP04250045A 2003-01-15 2004-01-07 Verfahren zur Herstellung eines Durchgangsloches Expired - Lifetime EP1439576B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003007461A JP4322508B2 (ja) 2003-01-15 2003-01-15 半導体装置の製造方法
JP2003007461 2003-01-15

Publications (3)

Publication Number Publication Date
EP1439576A2 EP1439576A2 (de) 2004-07-21
EP1439576A3 true EP1439576A3 (de) 2007-04-25
EP1439576B1 EP1439576B1 (de) 2012-02-22

Family

ID=32588516

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04250045A Expired - Lifetime EP1439576B1 (de) 2003-01-15 2004-01-07 Verfahren zur Herstellung eines Durchgangsloches

Country Status (3)

Country Link
US (1) US6831000B2 (de)
EP (1) EP1439576B1 (de)
JP (1) JP4322508B2 (de)

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US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
JP4850392B2 (ja) 2004-02-17 2012-01-11 三洋電機株式会社 半導体装置の製造方法
TWI303491B (en) * 2004-02-20 2008-11-21 Toshiba Kk Semiconductor relay apparatus and wiring board fabrication method
JP4556454B2 (ja) * 2004-03-15 2010-10-06 パナソニック電工株式会社 半導体装置の製造方法
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) * 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7425499B2 (en) 2004-08-24 2008-09-16 Micron Technology, Inc. Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
SG120200A1 (en) 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
CN100525097C (zh) * 2004-09-13 2009-08-05 精工爱普生株式会社 电子零件和电子零件的制造方法
JP2006109400A (ja) 2004-09-13 2006-04-20 Seiko Epson Corp 電子部品、回路基板、電子機器、電子部品の製造方法
TWI303864B (en) * 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same
JP4443379B2 (ja) 2004-10-26 2010-03-31 三洋電機株式会社 半導体装置の製造方法
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
JP4434965B2 (ja) * 2005-01-11 2010-03-17 株式会社東芝 半導体装置
US20060160346A1 (en) * 2005-01-19 2006-07-20 Intel Corporation Substrate bump formation
US20060177999A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces
US7485967B2 (en) 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
TW200644261A (en) * 2005-06-06 2006-12-16 Megica Corp Chip-package structure and manufacturing process thereof
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7884483B2 (en) 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
JP4758712B2 (ja) * 2005-08-29 2011-08-31 新光電気工業株式会社 半導体装置の製造方法
JP4533283B2 (ja) 2005-08-29 2010-09-01 新光電気工業株式会社 半導体装置の製造方法
JP4828182B2 (ja) * 2005-08-31 2011-11-30 新光電気工業株式会社 半導体装置の製造方法
US7622377B2 (en) 2005-09-01 2009-11-24 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7772115B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure
JP4536629B2 (ja) * 2005-09-21 2010-09-01 新光電気工業株式会社 半導体チップの製造方法
US8154105B2 (en) * 2005-09-22 2012-04-10 International Rectifier Corporation Flip chip semiconductor device and process of its manufacture
WO2007083748A1 (ja) * 2006-01-19 2007-07-26 Fujikura Ltd. 圧力センサパッケージ及び電子部品
US7892972B2 (en) * 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
EP2097924A4 (de) * 2006-12-29 2012-01-04 Cufer Asset Ltd Llc Front-end-verarbeiteter wafer mit verbindungen durch chip
JP4353263B2 (ja) * 2007-03-16 2009-10-28 セイコーエプソン株式会社 半導体装置の製造方法及び半導体装置
KR100897761B1 (ko) 2007-05-21 2009-05-15 박태석 관통 비아홀 공정을 이용한 실리콘 이미지 센서의 웨이퍼레벨 패키지 및 그 제조방법
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
KR100886720B1 (ko) * 2007-10-30 2009-03-04 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
JP4781440B2 (ja) * 2009-02-05 2011-09-28 ソニー エリクソン モバイル コミュニケーションズ， エービー 画像撮影装置、画像撮影装置の制御方法及び制御プログラム
US8415805B2 (en) * 2010-12-17 2013-04-09 Skyworks Solutions, Inc. Etched wafers and methods of forming the same
JP5313294B2 (ja) * 2011-05-16 2013-10-09 新光電気工業株式会社 半導体装置
US8975729B2 (en) * 2012-01-13 2015-03-10 Qualcomm Incorporated Integrating through substrate vias into middle-of-line layers of integrated circuits
JP5521130B1 (ja) * 2012-08-30 2014-06-11 パナソニック株式会社 電子部品パッケージおよびその製造方法
WO2014038128A1 (ja) 2012-09-05 2014-03-13 パナソニック株式会社 半導体装置およびその製造方法
JP7070848B2 (ja) 2018-07-26 2022-05-18 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP7176169B2 (ja) * 2019-02-28 2022-11-22 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法及び半導体装置
DE112020007877T5 (de) * 2020-12-22 2023-10-19 Mitsubishi Electric Corporation Halbleitervorrichtung und Verfahren zur deren Herstellung

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EP1267402A2 (de) * 2001-06-14 2002-12-18 Shinko Electric Industries Co. Ltd. Halbleiter und seine Herstellung

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Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
EP1267402A2 (de) * 2001-06-14 2002-12-18 Shinko Electric Industries Co. Ltd. Halbleiter und seine Herstellung

Also Published As

Publication number Publication date
US20040137661A1 (en) 2004-07-15
JP2004221357A (ja) 2004-08-05
JP4322508B2 (ja) 2009-09-02
US6831000B2 (en) 2004-12-14
EP1439576A2 (de) 2004-07-21
EP1439576B1 (de) 2012-02-22

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