ES2063818T3 - Aparato de tratamiento de datos con preextraccion selectiva de instrucciones. - Google Patents

Aparato de tratamiento de datos con preextraccion selectiva de instrucciones.

Info

Publication number
ES2063818T3
ES2063818T3 ES89305306T ES89305306T ES2063818T3 ES 2063818 T3 ES2063818 T3 ES 2063818T3 ES 89305306 T ES89305306 T ES 89305306T ES 89305306 T ES89305306 T ES 89305306T ES 2063818 T3 ES2063818 T3 ES 2063818T3
Authority
ES
Spain
Prior art keywords
hidden
addresses
microprocessor
bus
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89305306T
Other languages
English (en)
Inventor
Ralph Murray Begun
Patrick Maurice Bland
Mark Edward Dean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2063818T3 publication Critical patent/ES2063818T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)

Abstract

EN UN MICROCOMPUTADOR QUE CONSTA DE UN MICROPROCESADOR Y UN SUBSISTEMA OCULTO Y QUE PUEDE HACERSE FUNCIONAR EN UN MODO DE CANALIZACION, EXISTE UNA INCOMPATIBILIDAD POTENCIAL ENTRE LAS OPERACIONES DE CANALIZACION Y EL DIMENSIONAMIENTO DINAMICO DEL BUS YA QUE EL SUBSISTEMA OCULTO OPERA CON UNA LONGITUD FIJA DE DATOS Y EL DIMENSIONAMIENTO DINAMICO DEL BUS PERMITE QUE EL SISTEMA OPERE CON DISPOSITIVOS DE DISTINTAS LONGITUDES DE DATOS. ESTA INCOMPATIBILIDAD SE SUPERA POR EL PRESENTE SISTEMA DEFINIENDO CIERTAS DIRECCIONES COMO DIRECCIONES OCULTABLES Y OTRAS DIRECCIONES COMO DIRECCIONES NO OCULTABLES Y ASEGURANDO QUE NO SE OCULTAN LAS DIRECCIONES DE LOS DISPOSITIVOS DE LONGITUDUD DE DATOS DISTINTA A LA DE LOS DATOS OCULTOS. UN DECODIFICADOR DE DIRECCION PROPORCIONA UNA SEÑAL DE CONTROL QUE INDICA SI LA DIRECCION GENERADA ES OCULTABLE O NO. ESTA SEÑAL DE CONTROL CONTROLA LA SEÑAL DE DIRECCION SIGUIENTE APLICADA AL MICROPROCESADOR, LA CUAL PERMITE QUE EL MICROPROCESADOR INICIA EL SIGUIENTE CICLOANTES DE QUE FINALICE EL CICLO EN CURSO. SIEMPRE QUE SE DETECTA UNA SEÑAL NO OCULTABLE, SE SUPRIME LA SIGUIENTE SEÑAL DE DIRECCION.
ES89305306T 1988-05-26 1989-05-25 Aparato de tratamiento de datos con preextraccion selectiva de instrucciones. Expired - Lifetime ES2063818T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/198,894 US5125084A (en) 1988-05-26 1988-05-26 Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller

Publications (1)

Publication Number Publication Date
ES2063818T3 true ES2063818T3 (es) 1995-01-16

Family

ID=22735315

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89305306T Expired - Lifetime ES2063818T3 (es) 1988-05-26 1989-05-25 Aparato de tratamiento de datos con preextraccion selectiva de instrucciones.

Country Status (25)

Country Link
US (1) US5125084A (es)
EP (1) EP0343988B1 (es)
JP (1) JPH0623960B2 (es)
KR (1) KR930002321B1 (es)
CN (1) CN1009589B (es)
AR (1) AR242671A1 (es)
AT (1) ATE112869T1 (es)
AU (1) AU615055B2 (es)
BE (1) BE1002768A4 (es)
BR (1) BR8902393A (es)
CA (1) CA1313274C (es)
DE (2) DE3914265A1 (es)
DK (1) DK169492B1 (es)
ES (1) ES2063818T3 (es)
FI (1) FI95175C (es)
FR (1) FR2632090A1 (es)
GB (2) GB8904921D0 (es)
HK (1) HK11492A (es)
IT (1) IT1230207B (es)
MX (1) MX173139B (es)
MY (1) MY104738A (es)
NL (1) NL8901326A (es)
NO (1) NO174788B (es)
SE (1) SE8901307L (es)
SG (1) SG110691G (es)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2504206B2 (ja) * 1989-07-27 1996-06-05 三菱電機株式会社 バスコントロ―ラ
CA2023998A1 (en) * 1989-11-13 1991-05-14 Thomas F. Lewis Apparatus and method for guaranteeing strobe separation timing
US5517626A (en) * 1990-05-07 1996-05-14 S3, Incorporated Open high speed bus for microcomputer system
JP3215105B2 (ja) * 1990-08-24 2001-10-02 富士通株式会社 メモリアクセス装置
GB9018992D0 (en) * 1990-08-31 1990-10-17 Ncr Co Internal bus for work station interfacing means
US5274763A (en) * 1990-12-28 1993-12-28 Apple Computer, Inc. Data path apparatus for IO adapter
CA2060820C (en) * 1991-04-11 1998-09-15 Mick R. Jacobs Direct memory access for data transfer within an i/o device
GB2256296B (en) * 1991-05-31 1995-01-18 Integrated Device Tech Multiplexed status and diagnostic pins in a microprocessor with on-chip caches
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
US5630163A (en) * 1991-08-09 1997-05-13 Vadem Corporation Computer having a single bus supporting multiple bus architectures operating with different bus parameters
JP2599539B2 (ja) * 1991-10-15 1997-04-09 インターナショナル・ビジネス・マシーンズ・コーポレイション 直接メモリ・アクセス装置及びルック・アヘッド装置
JP2836321B2 (ja) * 1991-11-05 1998-12-14 三菱電機株式会社 データ処理装置
US5317712A (en) * 1991-12-19 1994-05-31 Intel Corporation Method and apparatus for testing and configuring the width of portions of a memory
JPH07504773A (ja) * 1992-03-18 1995-05-25 セイコーエプソン株式会社 マルチ幅のメモリ・サブシステムをサポートするためのシステム並びに方法
US5307475A (en) * 1992-06-29 1994-04-26 The United States Of America As Represented By The Secretary Of The Navy Slave controller utilizing eight least/most significant bits for accessing sixteen bit data words
US5313593A (en) * 1992-09-17 1994-05-17 International Business Machines Corp. Personal computer system with bus noise rejection
JPH0827773B2 (ja) * 1992-10-23 1996-03-21 インターナショナル・ビジネス・マシーンズ・コーポレイション データ経路を使用可能にする方法、装置およびデータ処理システム
JP3369227B2 (ja) * 1992-11-09 2003-01-20 株式会社東芝 プロセッサ
JP3904244B2 (ja) 1993-09-17 2007-04-11 株式会社ルネサステクノロジ シングル・チップ・データ処理装置
JPH07210537A (ja) * 1993-12-10 1995-08-11 Advanced Micro Devicds Inc コンピュータシステム
US5835960A (en) * 1994-01-07 1998-11-10 Cirrus Logic, Inc. Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus
US5548733A (en) * 1994-03-01 1996-08-20 Intel Corporation Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system
US5784579A (en) * 1994-03-01 1998-07-21 Intel Corporation Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
US5842041A (en) * 1994-05-20 1998-11-24 Advanced Micro Devices, Inc. Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus
JP3153078B2 (ja) * 1994-09-09 2001-04-03 日本電気株式会社 データ処理装置
JP2630271B2 (ja) * 1994-09-14 1997-07-16 日本電気株式会社 情報処理装置
US5890216A (en) * 1995-04-21 1999-03-30 International Business Machines Corporation Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
US5758188A (en) * 1995-11-21 1998-05-26 Quantum Corporation Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal
US6504854B1 (en) 1998-04-10 2003-01-07 International Business Machines Corporation Multiple frequency communications
US6725348B1 (en) * 1999-10-13 2004-04-20 International Business Machines Corporation Data storage device and method for reducing write misses by completing transfer to a dual-port cache before initiating a disk write of the data from the cache
JP3857661B2 (ja) * 2003-03-13 2006-12-13 インターナショナル・ビジネス・マシーンズ・コーポレーション 情報処理装置、プログラム、及び記録媒体
US7366864B2 (en) * 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
US8825962B1 (en) 2010-04-20 2014-09-02 Facebook, Inc. Push-based cache invalidation notification
CN113514408B (zh) * 2021-06-28 2024-06-11 杭州谱育科技发展有限公司 具有校正功能的臭氧检测装置及方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016541A (en) * 1972-10-10 1977-04-05 Digital Equipment Corporation Memory unit for connection to central processor unit and interconnecting bus
US4314334A (en) * 1977-08-30 1982-02-02 Xerox Corporation Serial data communication system having simplex/duplex interface
US4257095A (en) * 1978-06-30 1981-03-17 Intel Corporation System bus arbitration, circuitry and methodology
US4315308A (en) * 1978-12-21 1982-02-09 Intel Corporation Interface between a microprocessor chip and peripheral subsystems
US4480307A (en) * 1982-01-04 1984-10-30 Intel Corporation Interface for use between a memory and components of a module switching apparatus
US4503534A (en) * 1982-06-30 1985-03-05 Intel Corporation Apparatus for redundant operation of modules in a multiprocessing system
US4649476A (en) * 1983-10-31 1987-03-10 Motorola, Inc. Microcomputer having an internal address mapper
JPS6240555A (ja) * 1985-08-16 1987-02-21 Fujitsu Ltd プリフエツチ制御方式
US4853846A (en) * 1986-07-29 1989-08-01 Intel Corporation Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors
GB2200483B (en) * 1987-01-22 1991-10-16 Nat Semiconductor Corp Memory referencing in a high performance microprocessor
US4933845A (en) * 1987-09-04 1990-06-12 Digital Equipment Corporation Reconfigurable bus
EP0309995B1 (en) * 1987-09-28 1994-11-30 Compaq Computer Corporation System for fast selection of non-cacheable address ranges using programmed array logic
CA1314104C (en) * 1987-09-28 1993-03-02 Paul R. Culley Executing code from slow rom on high speed computer compatible with slower speed computers

Also Published As

Publication number Publication date
US5125084A (en) 1992-06-23
BR8902393A (pt) 1990-01-16
DK189489A (da) 1989-11-27
FI891787A7 (fi) 1989-11-27
EP0343988A2 (en) 1989-11-29
FI891787A0 (fi) 1989-04-14
NO174788B (no) 1994-03-28
NO891584L (no) 1989-11-27
MX173139B (es) 1994-02-02
GB8904921D0 (en) 1989-04-12
EP0343988A3 (en) 1991-01-30
JPH02146645A (ja) 1990-06-05
SE8901307D0 (sv) 1989-04-11
IT8920648A0 (it) 1989-05-25
DE68918754D1 (de) 1994-11-17
NL8901326A (nl) 1989-12-18
DE3914265C2 (es) 1992-01-09
FI95175B (fi) 1995-09-15
HK11492A (en) 1992-02-21
BE1002768A4 (fr) 1991-06-04
CN1037976A (zh) 1989-12-13
SE8901307L (sv) 1989-11-27
NO891584D0 (no) 1989-04-18
AU615055B2 (en) 1991-09-19
SG110691G (en) 1992-02-14
DK189489D0 (da) 1989-04-19
AR242671A1 (es) 1993-04-30
FR2632090A1 (fr) 1989-12-01
GB2219110B (en) 1991-02-20
DE3914265A1 (de) 1989-11-30
NO174788C (es) 1994-07-13
MY104738A (en) 1994-05-31
ATE112869T1 (de) 1994-10-15
FI95175C (fi) 1995-12-27
GB2219110A (en) 1989-11-29
CN1009589B (zh) 1990-09-12
IT1230207B (it) 1991-10-18
AU3409989A (en) 1989-11-30
GB8912018D0 (en) 1989-07-12
CA1313274C (en) 1993-01-26
JPH0623960B2 (ja) 1994-03-30
DK169492B1 (da) 1994-11-07
KR930002321B1 (ko) 1993-03-29
DE68918754T2 (de) 1995-04-27
KR890017604A (ko) 1989-12-16
EP0343988B1 (en) 1994-10-12

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