ES2069229T3 - Circuito bloqueado en fase y multiplicador de frecuencia como resultante. - Google Patents
Circuito bloqueado en fase y multiplicador de frecuencia como resultante.Info
- Publication number
- ES2069229T3 ES2069229T3 ES91400225T ES91400225T ES2069229T3 ES 2069229 T3 ES2069229 T3 ES 2069229T3 ES 91400225 T ES91400225 T ES 91400225T ES 91400225 T ES91400225 T ES 91400225T ES 2069229 T3 ES2069229 T3 ES 2069229T3
- Authority
- ES
- Spain
- Prior art keywords
- frequency multiplier
- phase
- result
- blocked circuit
- phase blocked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
EL MULTIPLICADOR DE FRECUENCIA 20 ESTA FORMADO POR UN CIRCUITO BLOQUEADO EN FASE QUE CONSTA DE UN COMPARADOR DE FASE 11 PARA MANDAR UNA PLURALIDAD DE ELEMENTOS DE RETRASO 130-137 QUE EMITEN UNAS SEÑALES DESFASADAS SUCESIVAMENTE EN FASE CL0-CL7 A UN ADICIONADOR LOGICO 16 HECHO DE PUERTAS OU EXCLUSIVO.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR909001366A FR2658015B1 (fr) | 1990-02-06 | 1990-02-06 | Circuit verrouille en phase et multiplieur de frequence en resultant. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2069229T3 true ES2069229T3 (es) | 1995-05-01 |
Family
ID=9393432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES91400225T Expired - Lifetime ES2069229T3 (es) | 1990-02-06 | 1991-01-30 | Circuito bloqueado en fase y multiplicador de frecuencia como resultante. |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US5260608A (es) |
| EP (1) | EP0441684B1 (es) |
| JP (1) | JP3098027B2 (es) |
| CA (1) | CA2051121C (es) |
| DE (1) | DE69106159T2 (es) |
| ES (1) | ES2069229T3 (es) |
| FR (1) | FR2658015B1 (es) |
| WO (1) | WO1991012666A1 (es) |
Families Citing this family (86)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6150855A (en) * | 1990-02-06 | 2000-11-21 | Bull, S.A. | Phase-locked loop and resulting frequency multiplier |
| FR2689339B1 (fr) * | 1992-03-24 | 1996-12-13 | Bull Sa | Procede et dispositif de reglage de retard a plusieurs gammes. |
| BR9305935A (pt) * | 1992-12-23 | 1997-08-26 | Comstream Corp | Comutador de fase controlada digitalmente |
| US5422835A (en) * | 1993-07-28 | 1995-06-06 | International Business Machines Corporation | Digital clock signal multiplier circuit |
| FR2710800B1 (fr) * | 1993-09-27 | 1995-12-15 | Sgs Thomson Microelectronics | Ligne à retard numérique. |
| US5463337A (en) * | 1993-11-30 | 1995-10-31 | At&T Corp. | Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein |
| FR2714550B1 (fr) * | 1993-12-24 | 1996-02-02 | Bull Sa | Arbre de portes logiques OU-Exclusif et multiplieur de fréquence l'incorporant. |
| DE4422802C1 (de) * | 1994-06-29 | 1995-07-20 | Siemens Ag | Schaltungsanordnung zur Frequenzvervielfachung |
| FR2723494B1 (fr) | 1994-08-04 | 1996-09-06 | Bull Sa | Procede d'echantillonnage d'un signal numerique en serie |
| US5815016A (en) * | 1994-09-02 | 1998-09-29 | Xilinx, Inc. | Phase-locked delay loop for clock correction |
| US5646564A (en) * | 1994-09-02 | 1997-07-08 | Xilinx, Inc. | Phase-locked delay loop for clock correction |
| US5640523A (en) * | 1994-09-02 | 1997-06-17 | Cypress Semiconductor Corporation | Method and apparatus for a pulsed tri-state phase detector for reduced jitter clock recovery |
| US5537068A (en) * | 1994-09-06 | 1996-07-16 | Intel Corporation | Differential delay line clock generator |
| US5828250A (en) * | 1994-09-06 | 1998-10-27 | Intel Corporation | Differential delay line clock generator with feedback phase control |
| US5455540A (en) * | 1994-10-26 | 1995-10-03 | Cypress Semiconductor Corp. | Modified bang-bang phase detector with ternary output |
| US5506520A (en) * | 1995-01-11 | 1996-04-09 | International Business Machines Corporation | Energy conserving clock pulse generating circuits |
| US5832279A (en) * | 1995-06-07 | 1998-11-03 | Lsi Logic Corporation | Advanced programmable interrupt controller (APIC) with high speed serial data bus |
| US5721501A (en) * | 1995-07-26 | 1998-02-24 | Kabushiki Kaisha Toshiba | Frequency multiplier and semiconductor integrated circuit employing the same |
| JP3561792B2 (ja) * | 1995-09-06 | 2004-09-02 | 株式会社ルネサステクノロジ | クロック発生回路 |
| US5825824A (en) * | 1995-10-05 | 1998-10-20 | Silicon Image, Inc. | DC-balanced and transition-controlled encoding method and apparatus |
| US5999571A (en) * | 1995-10-05 | 1999-12-07 | Silicon Image, Inc. | Transition-controlled digital encoding and signal transmission system |
| US5974464A (en) * | 1995-10-06 | 1999-10-26 | Silicon Image, Inc. | System for high speed serial video signal transmission using DC-balanced coding |
| US5744991A (en) * | 1995-10-16 | 1998-04-28 | Altera Corporation | System for distributing clocks using a delay lock loop in a programmable logic circuit |
| US5786732A (en) * | 1995-10-24 | 1998-07-28 | Vlsi Technology, Inc. | Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit |
| US5614868A (en) * | 1995-10-24 | 1997-03-25 | Vlsi Technology, Inc. | Phase locked loop having voltage controlled oscillator utilizing combinational logic |
| JP3323054B2 (ja) * | 1996-04-01 | 2002-09-09 | 株式会社東芝 | 周波数逓倍回路 |
| JP3442924B2 (ja) * | 1996-04-01 | 2003-09-02 | 株式会社東芝 | 周波数逓倍回路 |
| WO1997040576A1 (en) * | 1996-04-25 | 1997-10-30 | Credence Systems Corporation | Frequency multiplier |
| US5786715A (en) * | 1996-06-21 | 1998-07-28 | Sun Microsystems, Inc. | Programmable digital frequency multiplier |
| JPH1022822A (ja) * | 1996-07-05 | 1998-01-23 | Sony Corp | ディジタルpll回路 |
| US5821785A (en) * | 1996-08-02 | 1998-10-13 | Rockwell Int'l Corp. | Clock signal frequency multiplier |
| TW340262B (en) | 1996-08-13 | 1998-09-11 | Fujitsu Ltd | Semiconductor device, system consisting of semiconductor devices and digital delay circuit |
| GB2355095B (en) * | 1996-08-13 | 2001-05-23 | Fujitsu Ltd | Semiconductor circuitry |
| JPH10117142A (ja) * | 1996-10-11 | 1998-05-06 | Fujitsu Ltd | 位相同期ループ回路および半導体集積回路 |
| US5933035A (en) * | 1996-12-31 | 1999-08-03 | Cirrus Logic, Inc. | Digital clock frequency multiplication circuit and method |
| KR100214559B1 (ko) * | 1997-02-20 | 1999-08-02 | 구본준 | 주파수 배가기 |
| JPH10256883A (ja) * | 1997-03-06 | 1998-09-25 | Nec Ic Microcomput Syst Ltd | デジタル逓倍回路 |
| JP2954070B2 (ja) * | 1997-03-26 | 1999-09-27 | 日本電気アイシーマイコンシステム株式会社 | デジタルpll回路 |
| JP3319340B2 (ja) | 1997-05-30 | 2002-08-26 | 日本電気株式会社 | 半導体回路装置 |
| US6100736A (en) * | 1997-06-05 | 2000-08-08 | Cirrus Logic, Inc | Frequency doubler using digital delay lock loop |
| US5889435A (en) * | 1997-06-30 | 1999-03-30 | Sun Microsystems, Inc. | On-chip PLL phase and jitter self-test circuit |
| FR2766305B1 (fr) * | 1997-07-16 | 2004-01-02 | St Microelectronics Sa | Procede de multiplication de la frequence d'un signal d'horloge avec controle du rapport cyclique, et dispositif correspondant |
| JPH11110065A (ja) | 1997-10-03 | 1999-04-23 | Mitsubishi Electric Corp | 内部クロック信号発生回路 |
| FR2770704B1 (fr) * | 1997-11-03 | 2000-04-14 | Sgs Thomson Microelectronics | Circuit verrouille en phase |
| US5982213A (en) * | 1997-11-14 | 1999-11-09 | Texas Instruments Incorporated | Digital phase lock loop |
| US6023182A (en) * | 1997-12-31 | 2000-02-08 | Intel Corporation | High gain pulse generator circuit with clock gating |
| US5963071A (en) * | 1998-01-22 | 1999-10-05 | Nanoamp Solutions, Inc. | Frequency doubler with adjustable duty cycle |
| JP3338367B2 (ja) * | 1998-03-25 | 2002-10-28 | 沖電気工業株式会社 | 位相比較器 |
| JPH11298306A (ja) * | 1998-04-16 | 1999-10-29 | Nec Corp | 半導体装置および遅延設定方法 |
| US6037812A (en) * | 1998-05-18 | 2000-03-14 | National Semiconductor Corporation | Delay locked loop (DLL) based clock synthesis |
| US7564283B1 (en) | 1998-06-22 | 2009-07-21 | Xilinx, Inc. | Automatic tap delay calibration for precise digital phase shift |
| US6040726A (en) * | 1998-09-14 | 2000-03-21 | Lucent Technologies Inc. | Digital duty cycle correction loop apparatus and method |
| US6255878B1 (en) | 1998-09-18 | 2001-07-03 | Lsi Logic Corporation | Dual path asynchronous delay circuit |
| JP3271602B2 (ja) * | 1999-02-17 | 2002-04-02 | 日本電気株式会社 | 半導体集積回路装置およびその設計方法 |
| CA2270516C (en) * | 1999-04-30 | 2009-11-17 | Mosaid Technologies Incorporated | Frequency-doubling delay locked loop |
| US6211708B1 (en) * | 1999-06-28 | 2001-04-03 | Ericsson, Inc. | Frequency doubling circuits, method, and systems including quadrature phase generators |
| EP1076435A1 (en) * | 1999-08-12 | 2001-02-14 | STMicroelectronics S.r.l. | A detector for detecting timing in a data flow |
| US6275072B1 (en) * | 1999-10-07 | 2001-08-14 | Velio Communications, Inc. | Combined phase comparator and charge pump circuit |
| EP1094608B1 (en) * | 1999-10-18 | 2005-12-28 | STMicroelectronics S.r.l. | An improved delay-locked loop circuit |
| US6594330B1 (en) | 1999-10-26 | 2003-07-15 | Agere Systems Inc. | Phase-locked loop with digitally controlled, frequency-multiplying oscillator |
| US6674772B1 (en) * | 1999-10-28 | 2004-01-06 | Velio Communicaitons, Inc. | Data communications circuit with multi-stage multiplexing |
| US6952431B1 (en) | 1999-10-28 | 2005-10-04 | Rambus Inc. | Clock multiplying delay-locked loop for data communications |
| EP1250638B1 (en) * | 2000-01-24 | 2008-07-16 | Broadcom Corporation | System and method for compensating for supply voltage induced signal delay mismatches |
| JP3961195B2 (ja) * | 2000-05-30 | 2007-08-22 | 株式会社東芝 | 半導体集積回路 |
| US6768356B1 (en) * | 2000-09-07 | 2004-07-27 | Iowa State University Research Foundation, Inc. | Apparatus for and method of implementing time-interleaved architecture |
| DE10057905A1 (de) * | 2000-11-21 | 2002-06-06 | Micronas Gmbh | Phasenregelkreis mit Verzögerungselement |
| FR2817981B1 (fr) | 2000-12-07 | 2003-02-14 | Bull Sa | Circuit multiplieur de fronts |
| US6535038B2 (en) | 2001-03-09 | 2003-03-18 | Micron Technology, Inc. | Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices |
| US20040232954A1 (en) * | 2001-07-06 | 2004-11-25 | Van Zeijl Paulus Thomas | Signal generator device, method for generating a signal and devices including such a signal generator device |
| US6727764B2 (en) * | 2002-03-08 | 2004-04-27 | Sirific Wireless Corporation | Generation of virtual local oscillator inputs for use in direct conversion radio systems |
| CA2375291C (en) * | 2002-03-08 | 2005-05-17 | Sirific Wireless Corporation | Generation of virtual local oscillator inputs for use in direct conversion radio systems |
| US6653876B2 (en) * | 2002-04-23 | 2003-11-25 | Broadcom Corporation | Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL) |
| US6996650B2 (en) * | 2002-05-16 | 2006-02-07 | International Business Machines Corporation | Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus |
| US6880026B2 (en) * | 2002-05-16 | 2005-04-12 | International Business Machines Corporation | Method and apparatus for implementing chip-to-chip interconnect bus initialization |
| US8340215B2 (en) * | 2002-07-26 | 2012-12-25 | Motorola Mobility Llc | Radio transceiver architectures and methods |
| CN1689229A (zh) * | 2002-10-16 | 2005-10-26 | 皇家飞利浦电子股份有限公司 | 脉冲发生器 |
| US7372928B1 (en) | 2002-11-15 | 2008-05-13 | Cypress Semiconductor Corporation | Method and system of cycle slip framing in a deserializer |
| US8085857B1 (en) | 2003-09-25 | 2011-12-27 | Cypress Semiconductor Corporation | Digital-compatible multi-state-sense input |
| ATE364259T1 (de) * | 2003-12-10 | 2007-06-15 | Ericsson Telefon Ab L M | Frequenzvervielfacher |
| US7123063B2 (en) * | 2004-04-28 | 2006-10-17 | Broadcom Corporation | Supply tracking clock multiplier |
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| KR100693895B1 (ko) | 2005-08-16 | 2007-03-12 | 삼성전자주식회사 | 위상동기루프 회로를 구비한 클럭 체배기 |
| EP1833173A1 (en) * | 2006-03-06 | 2007-09-12 | Seiko Epson Corporation | Pulse generator and method of genrerating pulses, such as for template generation in impulse radio systems |
| US7719338B2 (en) * | 2007-06-05 | 2010-05-18 | Seiko Epson Corporation | Pulse generating circuit and UWB communication system |
| DE102007057990B3 (de) * | 2007-12-03 | 2009-04-16 | Knorr-Bremse Systeme für Nutzfahrzeuge GmbH | Verfahren und Schaltungsanordnung zur Überwachung von durch elektrische Impulse angesteuerten Geräten |
| US9966937B2 (en) * | 2011-04-29 | 2018-05-08 | Marvell World Trade Ltd. | Frequency multipliers |
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| FI41662C (fi) * | 1964-06-09 | 1970-01-12 | Ericsson Telefon Ab L M | Laite pulssikoodimoduloitujen aikakertosignaalien vastaanottimessa |
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-
1990
- 1990-02-06 FR FR909001366A patent/FR2658015B1/fr not_active Expired - Fee Related
-
1991
- 1991-01-30 US US07/762,018 patent/US5260608A/en not_active Expired - Lifetime
- 1991-01-30 JP JP03503776A patent/JP3098027B2/ja not_active Expired - Fee Related
- 1991-01-30 WO PCT/FR1991/000058 patent/WO1991012666A1/fr not_active Ceased
- 1991-01-30 ES ES91400225T patent/ES2069229T3/es not_active Expired - Lifetime
- 1991-01-30 CA CA002051121A patent/CA2051121C/fr not_active Expired - Fee Related
- 1991-01-30 DE DE69106159T patent/DE69106159T2/de not_active Expired - Fee Related
- 1991-01-30 EP EP91400225A patent/EP0441684B1/fr not_active Expired - Lifetime
-
1994
- 1994-10-03 US US08/312,981 patent/US5548235A/en not_active Expired - Lifetime
-
1997
- 1997-08-29 US US08/921,334 patent/US5838178A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69106159T2 (de) | 1995-05-04 |
| US5548235A (en) | 1996-08-20 |
| FR2658015B1 (fr) | 1994-07-29 |
| CA2051121C (fr) | 1996-08-20 |
| US5838178A (en) | 1998-11-17 |
| WO1991012666A1 (fr) | 1991-08-22 |
| FR2658015A1 (fr) | 1991-08-09 |
| JP3098027B2 (ja) | 2000-10-10 |
| EP0441684B1 (fr) | 1994-12-28 |
| US5260608A (en) | 1993-11-09 |
| JPH04505539A (ja) | 1992-09-24 |
| CA2051121A1 (fr) | 1991-08-07 |
| DE69106159D1 (de) | 1995-02-09 |
| EP0441684A1 (fr) | 1991-08-14 |
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