ID18123A - Metoda untuk memanufaktur alat semi konduktor - Google Patents

Metoda untuk memanufaktur alat semi konduktor

Info

Publication number
ID18123A
ID18123A IDP972754A ID972754A ID18123A ID 18123 A ID18123 A ID 18123A ID P972754 A IDP972754 A ID P972754A ID 972754 A ID972754 A ID 972754A ID 18123 A ID18123 A ID 18123A
Authority
ID
Indonesia
Prior art keywords
semi conductor
manufacturing semi
conductor tools
tools
manufacturing
Prior art date
Application number
IDP972754A
Other languages
English (en)
Indonesian (id)
Inventor
Yoshiji Takamura
Akio Kawamura
Katsuji Iguchi
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of ID18123A publication Critical patent/ID18123A/id

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
IDP972754A 1996-08-29 1997-08-07 Metoda untuk memanufaktur alat semi konduktor ID18123A (id)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22890196A JP3386101B2 (ja) 1996-08-29 1996-08-29 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
ID18123A true ID18123A (id) 1998-03-05

Family

ID=16883642

Family Applications (1)

Application Number Title Priority Date Filing Date
IDP972754A ID18123A (id) 1996-08-29 1997-08-07 Metoda untuk memanufaktur alat semi konduktor

Country Status (8)

Country Link
US (1) US5795803A (ja)
EP (1) EP0827205A3 (ja)
JP (1) JP3386101B2 (ja)
KR (1) KR100231765B1 (ja)
ID (1) ID18123A (ja)
MY (1) MY123831A (ja)
SG (1) SG70595A1 (ja)
TW (1) TW332924B (ja)

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US5963801A (en) * 1996-12-19 1999-10-05 Lsi Logic Corporation Method of forming retrograde well structures and punch-through barriers using low energy implants
JPH10189762A (ja) * 1996-12-20 1998-07-21 Nec Corp 半導体装置およびその製造方法
US6555484B1 (en) * 1997-06-19 2003-04-29 Cypress Semiconductor Corp. Method for controlling the oxidation of implanted silicon
US6137142A (en) * 1998-02-24 2000-10-24 Sun Microsystems, Inc. MOS device structure and method for reducing PN junction leakage
US5963799A (en) * 1998-03-23 1999-10-05 Texas Instruments - Acer Incorporated Blanket well counter doping process for high speed/low power MOSFETs
KR100262011B1 (ko) * 1998-05-07 2000-07-15 김영환 트윈 웰의 형성 방법
KR100505610B1 (ko) * 1998-07-06 2005-09-26 삼성전자주식회사 레트로그레이드 웰을 갖는 반도체장치의 제조방법
KR100324931B1 (ko) * 1999-01-22 2002-02-28 박종섭 반도체장치 및 그의 제조방법
US6238982B1 (en) * 1999-04-13 2001-05-29 Advanced Micro Devices Multiple threshold voltage semiconductor device fabrication technology
JP4666700B2 (ja) * 1999-08-30 2011-04-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US6693331B2 (en) * 1999-11-18 2004-02-17 Intel Corporation Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation
US6362035B1 (en) * 2000-02-07 2002-03-26 Taiwan Semiconductor Manufacturing Company Channel stop ion implantation method for CMOS integrated circuits
JP4765014B2 (ja) * 2001-01-23 2011-09-07 富士電機株式会社 半導体集積回路装置およびその製造方法
JP2003060073A (ja) 2001-08-10 2003-02-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6879007B2 (en) * 2002-08-08 2005-04-12 Sharp Kabushiki Kaisha Low volt/high volt transistor
US6881634B2 (en) * 2002-08-30 2005-04-19 Cypress Semiconductor Corporation Buried-channel transistor with reduced leakage current
US7202133B2 (en) 2004-01-21 2007-04-10 Chartered Semiconductor Manufacturing, Ltd. Structure and method to form source and drain regions over doped depletion regions
KR100598033B1 (ko) * 2004-02-03 2006-07-07 삼성전자주식회사 반도체 소자의 듀얼 게이트 산화막 형성 방법
JP4511307B2 (ja) * 2004-02-10 2010-07-28 セイコーエプソン株式会社 ゲート絶縁膜、半導体素子、電子デバイスおよび電子機器
JP4540438B2 (ja) * 2004-09-27 2010-09-08 富士通セミコンダクター株式会社 半導体装置及びその製造方法
KR100697289B1 (ko) * 2005-08-10 2007-03-20 삼성전자주식회사 반도체 장치의 형성 방법
KR100710195B1 (ko) * 2005-12-28 2007-04-20 동부일렉트로닉스 주식회사 모스 버랙터의 제조 방법
JP2007281027A (ja) * 2006-04-03 2007-10-25 Renesas Technology Corp 半導体装置とその製造方法
JP2008153621A (ja) * 2006-11-22 2008-07-03 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2008270419A (ja) * 2007-04-18 2008-11-06 Nec Electronics Corp サンプルウェハの製造方法
JP2009182161A (ja) 2008-01-31 2009-08-13 Renesas Technology Corp 半導体装置
US7800179B2 (en) 2009-02-04 2010-09-21 Fairchild Semiconductor Corporation High speed, low power consumption, isolated analog CMOS unit
JP5374585B2 (ja) * 2009-06-05 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
FR2990563B1 (fr) * 2012-05-11 2014-05-09 Apollon Solar Cellule solaire a base de silicium dope de type n
JP6247463B2 (ja) * 2013-06-25 2017-12-13 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US10930507B2 (en) 2018-10-31 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Reduce well dopant loss in FinFETs through co-implantation
CN111430307B (zh) * 2019-12-17 2021-06-25 合肥晶合集成电路股份有限公司 半导体集成器件的阱制备方法和阱注入光罩组
US12527070B2 (en) * 2022-06-30 2026-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming wells for semiconductor devices using implanations of increasing energy

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5932163A (ja) * 1982-08-18 1984-02-21 Nec Corp Ｃｍｏｓ集積回路
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
JPS62254203A (ja) * 1986-04-23 1987-11-06 Daikin Ind Ltd 温度制御装置
JPS6388714A (ja) * 1986-10-02 1988-04-19 信越ポリマ−株式会社 印刷配線板
JPH0267755A (ja) * 1988-09-01 1990-03-07 Mitsubishi Electric Corp 半導体装置
NL8802219A (nl) * 1988-09-09 1990-04-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
JP2745228B2 (ja) * 1989-04-05 1998-04-28 三菱電機株式会社 半導体装置およびその製造方法
JPH02305468A (ja) * 1989-05-19 1990-12-19 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0468564A (ja) * 1990-07-10 1992-03-04 Sony Corp 半導体装置の製法
JP2851753B2 (ja) * 1991-10-22 1999-01-27 三菱電機株式会社 半導体装置およびその製造方法
JP2682425B2 (ja) * 1993-12-24 1997-11-26 日本電気株式会社 半導体装置の製造方法
US5416038A (en) * 1994-05-25 1995-05-16 United Microelectronics Corporation Method for producing semiconductor device with two different threshold voltages
US5501993A (en) * 1994-11-22 1996-03-26 Genus, Inc. Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation
US5489540A (en) * 1995-03-22 1996-02-06 Advanced Micro Devices Inc. Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask
US5654213A (en) * 1995-10-03 1997-08-05 Integrated Device Technology, Inc. Method for fabricating a CMOS device

Also Published As

Publication number Publication date
SG70595A1 (en) 2000-02-22
EP0827205A3 (en) 1998-09-23
KR19980018264A (ko) 1998-06-05
JP3386101B2 (ja) 2003-03-17
US5795803A (en) 1998-08-18
MY123831A (en) 2006-06-30
EP0827205A2 (en) 1998-03-04
KR100231765B1 (ko) 1999-11-15
TW332924B (en) 1998-06-01
JPH1074844A (ja) 1998-03-17

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