IT1245795B - Procedimento per la formazione di uno strato di ossido di campo di un dispositivo a semiconduttore - Google Patents

Procedimento per la formazione di uno strato di ossido di campo di un dispositivo a semiconduttore

Info

Publication number
IT1245795B
IT1245795B ITMI910735A ITMI910735A IT1245795B IT 1245795 B IT1245795 B IT 1245795B IT MI910735 A ITMI910735 A IT MI910735A IT MI910735 A ITMI910735 A IT MI910735A IT 1245795 B IT1245795 B IT 1245795B
Authority
IT
Italy
Prior art keywords
oxide layer
field
field oxide
formation
layer
Prior art date
Application number
ITMI910735A
Other languages
English (en)
Inventor
Weon-Sik Paek
Taek-Yong Jang
Weon-Taek Choi
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI910735A0 publication Critical patent/ITMI910735A0/it
Publication of ITMI910735A1 publication Critical patent/ITMI910735A1/it
Application granted granted Critical
Publication of IT1245795B publication Critical patent/IT1245795B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Procedimento per la formazione di uno strato di ossido di campo (36) consistente in:crescita di uno strato di ossido di pad (31) e deposizione di uno strato di nitruro (33);rimozione del nitruro (33) sopra la regione di campo; formazione di spaziatori (34) sulle pareti laterali del rimanente strato di nitruro;drogaggio delle regioni di campo;crescita di uno strato di ossido di campo (36) ossidando la porzione esposta del substrato nella regione di campo; planarizzazione dello strato di ossido di campo (36) con processo di retroattacco;riduzione dei problemi di copertura del gradino dello strato di ossido di campo (36).Vengono ridotti la dimensione del becco e lo stress ai margini della regione di campo. Lo strato di arresto del canale pesantemente drogato è formato solo nella regione mediana della regione di campo, prevenendo l'abbassamento della tensione di scarica e la perforazione.
ITMI910735A 1990-11-17 1991-03-19 Procedimento per la formazione di uno strato di ossido di campo di un dispositivo a semiconduttore IT1245795B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900018656A KR930011458B1 (ko) 1990-11-17 1990-11-17 반도체장치의 필드산화막 형성방법

Publications (3)

Publication Number Publication Date
ITMI910735A0 ITMI910735A0 (it) 1991-03-19
ITMI910735A1 ITMI910735A1 (it) 1992-09-19
IT1245795B true IT1245795B (it) 1994-10-18

Family

ID=19306174

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI910735A IT1245795B (it) 1990-11-17 1991-03-19 Procedimento per la formazione di uno strato di ossido di campo di un dispositivo a semiconduttore

Country Status (7)

Country Link
US (1) US5472905A (it)
JP (1) JP2812811B2 (it)
KR (1) KR930011458B1 (it)
DE (1) DE4109184C2 (it)
FR (1) FR2669467B1 (it)
GB (1) GB2249867B (it)
IT (1) IT1245795B (it)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262346A (en) * 1992-12-16 1993-11-16 International Business Machines Corporation Nitride polish stop for forming SOI wafers
US5670412A (en) * 1995-07-25 1997-09-23 Micron Technology, Inc. Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate
US5882985A (en) * 1995-10-10 1999-03-16 Advanced Micro Devices, Inc. Reduction of field oxide step height during semiconductor fabrication
KR100366612B1 (ko) * 1995-11-20 2003-03-03 삼성전자 주식회사 평탄화된필드절연막을갖는반도체장치의제조방법
US5780353A (en) * 1996-03-28 1998-07-14 Advanced Micro Devices, Inc. Method of doping trench sidewalls before trench etching
US6097072A (en) * 1996-03-28 2000-08-01 Advanced Micro Devices Trench isolation with suppressed parasitic edge transistors
US5904543A (en) * 1996-03-28 1999-05-18 Advanced Micro Devices, Inc Method for formation of offset trench isolation by the use of disposable spacer and trench oxidation
US5646063A (en) * 1996-03-28 1997-07-08 Advanced Micro Devices, Inc. Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device
US5861104A (en) * 1996-03-28 1999-01-19 Advanced Micro Devices Trench isolation with rounded top and bottom corners and edges
US5742090A (en) * 1996-04-04 1998-04-21 Advanced Micro Devices, Inc. Narrow width trenches for field isolation in integrated circuits
US5874317A (en) * 1996-06-12 1999-02-23 Advanced Micro Devices, Inc. Trench isolation for integrated circuits
US5777370A (en) 1996-06-12 1998-07-07 Advanced Micro Devices, Inc. Trench isolation of field effect transistors
US5652177A (en) * 1996-08-22 1997-07-29 Chartered Semiconductor Manufacturing Pte Ltd Method for fabricating a planar field oxide region
US5728614A (en) * 1996-09-25 1998-03-17 Vanguard International Semiconductor Corporation Method to improve the topography of a field oxide region
US6087239A (en) 1996-11-22 2000-07-11 Micron Technology, Inc. Disposable spacer and method of forming and using same
US5851901A (en) * 1997-04-11 1998-12-22 Advanced Micro Devices Method of manufacturing an isolation region of a semiconductor device with advanced planarization
US6184105B1 (en) 1997-05-22 2001-02-06 Advanced Micro Devices Method for post transistor isolation
JPH11214384A (ja) * 1998-01-28 1999-08-06 Mitsubishi Electric Corp 半導体装置の製造方法
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
US6727161B2 (en) 2000-02-16 2004-04-27 Cypress Semiconductor Corp. Isolation technology for submicron semiconductor devices
US7230745B1 (en) * 2002-04-08 2007-06-12 Captaris, Inc. Document transmission and routing with recipient control, such as facsimile document transmission and routing
US20070177195A1 (en) * 2005-10-31 2007-08-02 Treber Rebert Queue processor for document servers
US12003603B2 (en) * 2005-10-31 2024-06-04 Open Text Sa Ulc Queue processor for document servers
WO2007053717A2 (en) * 2005-10-31 2007-05-10 Captaris, Inc. Universal document transport
WO2008017048A2 (en) 2006-08-02 2008-02-07 Captaris, Inc. Configurable document server

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710246A (en) * 1980-03-06 1982-01-19 Toshiba Corp Manufacture of semiconductor device
JPS5735341A (en) * 1980-08-12 1982-02-25 Toshiba Corp Method of seperating elements of semiconductor device
JPS58147041A (ja) * 1982-02-24 1983-09-01 Fujitsu Ltd 半導体装置の製造方法
JPS6050939A (ja) * 1983-08-30 1985-03-22 Toshiba Corp 半導体装置の製造方法
US4631219A (en) * 1985-01-31 1986-12-23 International Business Machines Corporation Growth of bird's beak free semi-rox
JPS62232143A (ja) * 1986-04-01 1987-10-12 Toshiba Corp 半導体装置の製造方法
KR880008448A (ko) * 1986-12-17 1988-08-31 강진구 측면 격리 소자 분리방법
EP0284456B1 (en) * 1987-02-24 1991-09-25 STMicroelectronics, Inc. Pad oxide protect sealed interface isolation process
JPS63302536A (ja) * 1987-06-02 1988-12-09 Sanyo Electric Co Ltd 素子分離領域の形成方法
JPH0198246A (ja) * 1987-10-12 1989-04-17 Sony Corp 半導体装置の製造方法
JPH01256147A (ja) * 1988-04-05 1989-10-12 Sharp Corp 半導体装置の製造方法
JPH01282839A (ja) * 1988-05-09 1989-11-14 Nec Corp 素子分離の製造方法
JPH088298B2 (ja) * 1988-10-04 1996-01-29 沖電気工業株式会社 半導体素子の製造方法
JPH02117150A (ja) * 1988-10-27 1990-05-01 Nec Corp 半導体装置の製造方法
US4897364A (en) * 1989-02-27 1990-01-30 Motorola, Inc. Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions

Also Published As

Publication number Publication date
JPH04234146A (ja) 1992-08-21
ITMI910735A0 (it) 1991-03-19
ITMI910735A1 (it) 1992-09-19
KR920010829A (ko) 1992-06-27
GB2249867A (en) 1992-05-20
GB9105923D0 (en) 1991-05-08
US5472905A (en) 1995-12-05
FR2669467B1 (fr) 1997-07-04
JP2812811B2 (ja) 1998-10-22
FR2669467A1 (fr) 1992-05-22
GB2249867B (en) 1995-04-05
DE4109184C2 (de) 1995-12-21
KR930011458B1 (ko) 1993-12-08
DE4109184A1 (de) 1992-05-21

Similar Documents

Publication Publication Date Title
IT1245795B (it) Procedimento per la formazione di uno strato di ossido di campo di un dispositivo a semiconduttore
US6849507B2 (en) Process for manufacture of low voltage power MOSFET device
US5219777A (en) Metal oxide semiconductor field effect transistor and method of making the same
US8487368B2 (en) Low voltage power MOSFET device and process for its manufacture
US5814859A (en) Self-aligned transistor device including a patterned refracting dielectric layer
US5391907A (en) Semiconductor device with buried inverse T-type field region
US4373965A (en) Suppression of parasitic sidewall transistors in locos structures
US5073519A (en) Method of fabricating a vertical FET device with low gate to drain overlap capacitance
AU5545894A (en) Power mosfet in silicon carbide
US20020142523A1 (en) Method of fabricating semiconductor device having notched gate
KR20010048716A (ko) 자기 정렬 기술을 이용한 트렌치 게이트 전력 소자 제조방법
EP1280191A3 (en) A method to form elevated source/drain regions using polysilicon spacers
US5972777A (en) Method of forming isolation by nitrogen implant to reduce bird's beak
KR930011500B1 (ko) 반도체장치의 소자분리방법
TW288205B (en) Process of fabricating high-density flat cell mask read only memory
US6316299B1 (en) Formation of laterally diffused metal-oxide semiconductor device
KR20040061025A (ko) 이중 게이트 산화물 고전압 반도체 디바이스 및 이의 제조방법
CN119653807A (zh) 一种SiC沟槽终端结构制作方法
KR920000637B1 (ko) Mosfet 제조방법 및 그 소자
KR940006698B1 (ko) 반도체 소자의 제조방법
KR100414742B1 (ko) 반도체소자의소자분리절연막형성방법
KR100313958B1 (ko) 반도체소자 및 그의 제조방법
KR950000104B1 (ko) 반도체 소자 격리 방법 및 셀 구조
JPS57120371A (en) Manufacture of complementary type mos semiconductor
KR100261523B1 (ko) 실리콘온인슐레이터기판을사용한완전공핍형트랜지스터형성방법

Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970326