IT1255293B - Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione - Google Patents

Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione

Info

Publication number
IT1255293B
IT1255293B ITMI921295A ITMI921295A IT1255293B IT 1255293 B IT1255293 B IT 1255293B IT MI921295 A ITMI921295 A IT MI921295A IT MI921295 A ITMI921295 A IT MI921295A IT 1255293 B IT1255293 B IT 1255293B
Authority
IT
Italy
Prior art keywords
plane
equivalent
procedure
manufacture
memory device
Prior art date
Application number
ITMI921295A
Other languages
English (en)
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI921295A0 publication Critical patent/ITMI921295A0/it
Publication of ITMI921295A1 publication Critical patent/ITMI921295A1/it
Application granted granted Critical
Publication of IT1255293B publication Critical patent/IT1255293B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dicing (AREA)

Abstract

In un wafer o fetta di silicio avente la sua superficie principale ed il piano di orientamento equivalenti al piano (100) ed al piano (110), rispettivamente, la superficie principale di una piastrina di semiconduttore è equivalente al piano (100), e tutte le superfici laterali interne di un condensatore a solco formato nella piastrina di semiconduttore sono equivalenti al piano (100). I quattro piani laterali periferici della piastrina di semiconduttore sono atti ad essere equivalenti al piano (110). Perciò, lo spessore di una pellicola di ossido su ciascuna superficie laterale interna del condensatore a solco è reso uniforme. Inoltre, è possibile impedire incrinature provocate nella piastrina in corrispondenza del momento del taglio.
ITMI921295A 1991-05-27 1992-05-26 Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione IT1255293B (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP12150391 1991-05-27
JP4079908A JPH05109984A (ja) 1991-05-27 1992-04-01 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
ITMI921295A0 ITMI921295A0 (it) 1992-05-26
ITMI921295A1 ITMI921295A1 (it) 1993-11-26
IT1255293B true IT1255293B (it) 1995-10-26

Family

ID=26420894

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921295A IT1255293B (it) 1991-05-27 1992-05-26 Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione

Country Status (4)

Country Link
JP (1) JPH05109984A (it)
KR (1) KR920022511A (it)
DE (1) DE4217420A1 (it)
IT (1) IT1255293B (it)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000002249A2 (de) * 1998-07-02 2000-01-13 Infineon Technologies Ag Integrierte schaltungsanordnung mit p-n übergängen mit reduzierten defekten
US6674134B2 (en) 1998-10-15 2004-01-06 International Business Machines Corporation Structure and method for dual gate oxidation for CMOS technology
US6426254B2 (en) * 1999-06-09 2002-07-30 Infineon Technologies Ag Method for expanding trenches by an anisotropic wet etch
US6320215B1 (en) * 1999-07-22 2001-11-20 International Business Machines Corporation Crystal-axis-aligned vertical side wall device
US6150670A (en) * 1999-11-30 2000-11-21 International Business Machines Corporation Process for fabricating a uniform gate oxide of a vertical transistor
US6362040B1 (en) * 2000-02-09 2002-03-26 Infineon Technologies Ag Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates
US6335247B1 (en) * 2000-06-19 2002-01-01 Infineon Technologies Ag Integrated circuit vertical trench device and method of forming thereof
EP1292982A2 (en) * 2000-06-21 2003-03-19 Infineon Technologies North America Corp. Gate oxidation for vertical trench device
KR100450683B1 (ko) * 2002-09-04 2004-10-01 삼성전자주식회사 Ｓｏｉ 기판에 형성되는 에스램 디바이스
DE10255866B4 (de) * 2002-11-29 2006-11-23 Infineon Technologies Ag Verfahren und Strukturen zur Erhöhung der Strukturdichte und der Speicherkapazität in einem Halbleiterwafer
JP4320167B2 (ja) 2002-12-12 2009-08-26 忠弘 大見 半導体素子及びシリコン酸化窒化膜の製造方法
CN102779745B (zh) * 2012-07-23 2016-07-06 上海华虹宏力半导体制造有限公司 控制沟槽晶体管栅介质层厚度的方法
KR102150969B1 (ko) 2013-12-05 2020-10-26 삼성전자주식회사 반도체 장치 및 그 제조방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6156446A (ja) * 1984-08-28 1986-03-22 Toshiba Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
ITMI921295A1 (it) 1993-11-26
KR920022511A (ko) 1992-12-19
ITMI921295A0 (it) 1992-05-26
DE4217420A1 (de) 1992-12-03
JPH05109984A (ja) 1993-04-30

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