JPH0125227B2 - - Google Patents

Info

Publication number
JPH0125227B2
JPH0125227B2 JP16456780A JP16456780A JPH0125227B2 JP H0125227 B2 JPH0125227 B2 JP H0125227B2 JP 16456780 A JP16456780 A JP 16456780A JP 16456780 A JP16456780 A JP 16456780A JP H0125227 B2 JPH0125227 B2 JP H0125227B2
Authority
JP
Japan
Prior art keywords
capacitance
terminal
semiconductor integrated
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16456780A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5789231A (en
Inventor
Kyobumi Uchibori
Minoru Pponda
Akira Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16456780A priority Critical patent/JPS5789231A/ja
Publication of JPS5789231A publication Critical patent/JPS5789231A/ja
Publication of JPH0125227B2 publication Critical patent/JPH0125227B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP16456780A 1980-11-25 1980-11-25 Semiconductor circuit device Granted JPS5789231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16456780A JPS5789231A (en) 1980-11-25 1980-11-25 Semiconductor circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16456780A JPS5789231A (en) 1980-11-25 1980-11-25 Semiconductor circuit device

Publications (2)

Publication Number Publication Date
JPS5789231A JPS5789231A (en) 1982-06-03
JPH0125227B2 true JPH0125227B2 (cs) 1989-05-16

Family

ID=15795614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16456780A Granted JPS5789231A (en) 1980-11-25 1980-11-25 Semiconductor circuit device

Country Status (1)

Country Link
JP (1) JPS5789231A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010114687A1 (en) * 2009-03-30 2010-10-07 Megica Corporation Integrated circuit chip using top post-passivation technology and bottom structure technology

Also Published As

Publication number Publication date
JPS5789231A (en) 1982-06-03

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