JPH0183332U - - Google Patents

Info

Publication number
JPH0183332U
JPH0183332U JP1987179206U JP17920687U JPH0183332U JP H0183332 U JPH0183332 U JP H0183332U JP 1987179206 U JP1987179206 U JP 1987179206U JP 17920687 U JP17920687 U JP 17920687U JP H0183332 U JPH0183332 U JP H0183332U
Authority
JP
Japan
Prior art keywords
magnetoresistive element
chip
smooth
substrate
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987179206U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987179206U priority Critical patent/JPH0183332U/ja
Publication of JPH0183332U publication Critical patent/JPH0183332U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第１図〜第３図は本考案のモールド形磁気抵抗
素子の実施例を示す斜視図、第４図〜第６図は従
来のモールド形磁気抵抗素子の実施例を示す斜視
図である。 １，８……シリコン基板、２，９……強磁性薄
膜パターン、３，１０……引出し用電極、４，１
１……エポキシ系接着剤、５，１２……支持体、
６，１３……リード端子、７，１４……ボンデイ
ングワイヤー。

Claims (1)

    【実用新案登録請求の範囲】
  1. 平滑な絶縁基板又は半導体基板上に絶縁膜を形
    成して成る平滑基板上にパターン形成が成された
    磁気抵抗素子チツプとリードフレームとボンデイ
    ングワイヤーと前記チツプ固定用接着剤と外装用
    樹脂から構成されるモールド形磁気抵抗素子に於
    いて、前記磁気抵抗素子チツプのパターン面と反
    対面にあらかじめ高分子樹脂による接着層を設け
    たことを特徴とするモールド形磁気抵抗素子。
JP1987179206U 1987-11-24 1987-11-24 Pending JPH0183332U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987179206U JPH0183332U (ja) 1987-11-24 1987-11-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987179206U JPH0183332U (ja) 1987-11-24 1987-11-24

Publications (1)

Publication Number Publication Date
JPH0183332U true JPH0183332U (ja) 1989-06-02

Family

ID=31470771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987179206U Pending JPH0183332U (ja) 1987-11-24 1987-11-24

Country Status (1)

Country Link
JP (1) JPH0183332U (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984532A (ja) * 1982-11-08 1984-05-16 Hitachi Ltd 半導体装置の製造方法および半導体ウエ−ハ
JPS6132435A (ja) * 1984-07-24 1986-02-15 Nec Corp 半導体素子の取り付け方法
JPS61216371A (ja) * 1985-03-20 1986-09-26 Nec Corp モ−ルド形磁気抵抗素子

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984532A (ja) * 1982-11-08 1984-05-16 Hitachi Ltd 半導体装置の製造方法および半導体ウエ−ハ
JPS6132435A (ja) * 1984-07-24 1986-02-15 Nec Corp 半導体素子の取り付け方法
JPS61216371A (ja) * 1985-03-20 1986-09-26 Nec Corp モ−ルド形磁気抵抗素子

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