JPH0197560U - - Google Patents

Info

Publication number
JPH0197560U
JPH0197560U JP1987194337U JP19433787U JPH0197560U JP H0197560 U JPH0197560 U JP H0197560U JP 1987194337 U JP1987194337 U JP 1987194337U JP 19433787 U JP19433787 U JP 19433787U JP H0197560 U JPH0197560 U JP H0197560U
Authority
JP
Japan
Prior art keywords
semiconductor
integrally formed
semiconductor element
resin
circuit boards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987194337U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987194337U priority Critical patent/JPH0197560U/ja
Publication of JPH0197560U publication Critical patent/JPH0197560U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は、本考案の実施例で樹脂封止前の斜視
図、第２図は、第１図の―の断面図、第３図
は、本考案の断面図、第４図は、他の実施例の断
面図、第５図は、従来例の半導体モジユールの平
面図である。 １…回路基板、２…半導体素子、３…外部リー
ド、４…ワイヤー、５…放熱板、６…樹脂封止体
、７…ＤＩＰ型半導体装置、８…凹所。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子を複数個樹脂封止してなる半導体装
    置において、少なくとも１個以上の半導体素子を
    載置し、前記半導体素子が外側になるようにして
    、放熱板を挾持して一体的に形成されている２枚
    の回路基板と、前記一体的に形成された２枚の回
    路基板に電気的に接続されている外部リードとか
    ら構成され、前記外部リードの１部をのぞき、各
    構成要素を一体的に樹脂封止してなる事を特徴と
    する半導体装置。
JP1987194337U 1987-12-21 1987-12-21 Pending JPH0197560U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987194337U JPH0197560U (ja) 1987-12-21 1987-12-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987194337U JPH0197560U (ja) 1987-12-21 1987-12-21

Publications (1)

Publication Number Publication Date
JPH0197560U true JPH0197560U (ja) 1989-06-29

Family

ID=31485068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987194337U Pending JPH0197560U (ja) 1987-12-21 1987-12-21

Country Status (1)

Country Link
JP (1) JPH0197560U (ja)

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