JPH02123637U

JPH02123637U -

Info

Publication number: JPH02123637U
Application number: JP2965889U
Authority: JP
Priority date: 1989-03-15
Filing date: 1989-03-15
Publication date: 1990-10-11

Description

[Brief explanation of drawings]

第１図は本考案の実施例を示す順序付きブレー
ク回路の構成図である。１−１〜１−３……ラツチ回路、３……比較器
、５……バイナリ・アツプカウンタ、１０……出
力制御部、ＡＤ……実行アドレス、ＢＫ……ブレ
ーク信号、ＣＮＴ……カウントタイミング信号、
Ｓ３……一致信号。 FIG. 1 is a block diagram of an ordered break circuit showing an embodiment of the present invention. 1-1 to 1-3...Latch circuit, 3...Comparator, 5...Binary up counter, 10...Output control section, AD...Execution address, BK...Break signal, CNT...Count timing signal,
S3... Match signal.

Claims

[Claims for Utility Model Registration] In a program evaluation device that compares reference information representing a break condition with input information corresponding to the reference information, and outputs a signal corresponding to the comparison result when a predetermined condition is met. In a break circuit with an ordered break condition, a holding circuit that holds the break condition, and a comparison that compares whether the input information and the break condition output from the holding circuit match or do not match, and outputs a match signal when they match. and a counter circuit using the coincidence signal as a count clock, the ordered break circuit having a circuit configuration in which the output of the holding circuit is controlled by the output of the counter circuit.