JPH02224149A - Information processor - Google Patents

Abstract

PURPOSE:To quickly detect a stall state and to improve the processing efficiency of a system by recognizing the stall state if a memory access request is not generated within a short fixed time. CONSTITUTION:An element processor unit(EPU) 1, an I/O processor(IOP) 2, a main memory unit(MMU) 3, a system control unit(SCU) 4, and a diagnostic processor(DGP) 6 are connected to a system bus 5 and a stall detecting circuit 10 is connected correspondingly to the EPU 1 and the IOP 2. When a memory access request is generated from the EPU 1 and IOP 2 which are processors to the MMU 3, the circuit 10 starts the counting of machine cycles or their corresponding values, and when the count value exceeds a fixed value, recognizes that the corresponding processor is a stall state. Consequently, the stall state of the system can be quickly detected and the processing efficiency of the system can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used for information processing. The present invention relates to fault detection in a processing device, and more particularly to stall detection for detecting that a processing device is in a stalled state due to a hardware abnormality, program abnormality, or the like.

〔overview〕

The present invention, in an information processing device in which at least one main storage device and a processing device are connected to one system bus, starts counting when a main storage device access request is issued from the processing device, and performs the counting. By recognizing that the corresponding processing unit is in a stall state when the numerical value exceeds a certain value, the processing efficiency of the system is increased, and the state when a stall occurs is understood from the hardware side, and stall detection is performed. It is designed to improve abilities.

[Conventional technology]

In conventional stall detection, each processing device has a counting means, and if processing of one software instruction is not completed within a certain period of time, it is recognized as a stall state.

[Problem that the invention seeks to solve]

In the conventional stall state detection described above, depending on the software instruction processing, one software instruction may require a very long firmware execution time, so the time setting for determining a stall state must be set to a large value. There wasn't.

For this reason, the stall state is detected only after a considerable number of machine cycles have passed since the time when the stall occurred, so there is a drawback that information about the stall state is not retained in a hardware tracer or the like.

In addition, if a multiprocessor etc. enters a stall state while processing communication requests from other processors, it may take a long time for the processing requesting processor to detect the stall, resulting in a failure of the processing requesting processor. There is a problem in that it takes time to determine whether the system is in a state or not, which not only reduces the processing efficiency of the entire system, but also causes other processor systems to go down because it takes a long time to detect a stall.

Furthermore, since the stall detection means is included in its own processing device, there is a possibility that the stall detection means may not operate normally depending on the cause of the stall, so there is a problem that stall detection is not performed satisfactorily.

The present invention aims to eliminate these drawbacks, and provides a device that can improve system processing efficiency, enable the status of a stall to be seen from the hardware side, and improve stall detection ability. purpose.

[Means for solving problems]

The present invention provides an information processing device in which at least two or more main storage devices and processing devices are connected to one system bus, in which each of the processing devices is provided with a means for counting machine cycles or signals corresponding to machine cycles from the time when an access request is issued to the main storage device, and recognizing a stall state when this counting means exceeds a certain value. The present invention is characterized by comprising a stall detection circuit including means.

[Effect]

A stall detection circuit provided corresponding to the main storage device and the processing device starts counting machine cycles or their corresponding values when the processing device issues an access request to the main storage device, and the counted value exceeds a certain value. When this occurs, the corresponding processing device is recognized as being in a stalled state.

This makes it possible to detect system stall conditions early and improve system processing efficiency. Also, when a stall is detected, the hardware side can understand the stall condition, further improving stall detection ability. be able to.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the overall structure of an embodiment of the present invention, and FIG. 2 is a block diagram showing the structure of a stall detection circuit according to the embodiment of the present invention.

In the embodiment of the present invention, the system bus 5 includes an unit processor unit (EPU) 1 and an output processor (IOP) 2.
, a main memory unit (MMU) 3, a system control unit (SCU) and a diagnostic processor (DGP) 6
A stall detection circuit 10 is provided corresponding to the unit processor unit (EPU) 1 and the input/output processor (IOP) 2.

The stall detection circuit 10 includes a counter (#0HO1), a counter (#1) 102, and a counter (#1) 102.
0) 101 and an AND gate 104 connected to the counter (#lNO2).

The operation of the embodiment of the present invention configured as described above will be explained.

Bus usage right request signals BU5RQO and BUS are sent from the unit processor unit (EPU) 1 and the input/output processor (IOP) 2 to obtain the right to use the system bus 5.
Each RQI is connected to a system control unit (SC).
U) 4 and diagnostic processor (DGP) 6;
In contrast, the bus right permission signal BACPO1BACP
I is sent from the system control unit (SCU) 4 and diagnostic processor (DGP) 6 to the unit processor unit (EPU) L input/output processor (IOP) 2. unit processor unit) (EPU) 1, output processor (IOP) 2, main memory (MMU>3
When making a memory access request to the
1", and when the bus arbitration section in the system control unit (SCU) 4 returns the bus permission signal BACPO1BACP 1, the bus becomes available and the main memory unit (MMU) 3 A memory access request is made to the system bus 5 via the system bus 5.

Therefore, when accessing memory, it is necessary to use unit processor unit (EPU) 1 or input/output processor (I/O processor).
OP)2 bus usage right request signals BUSRQO, BUSR
QI and bus right permission signal BACPO1BACP 1
Both become "1".

Next, the stall detection circuit 10 according to the embodiment of the present invention will be explained with reference to FIG. A counter (#0) 101 and a counter (#1) 102 are counters that detect time-outs of the unit processor unit (EPU) L input/output processor (IOP) 2, respectively.

Here, stall detection for the unit processor unit (EPU) 1 will be explained. When unit processor unit (EPU) 1 accesses memory, bus usage right request No. 11 BUSRQO becomes "1", and then this request is granted by the bus arbitration section of system control unit (SCU) 4. , bus permission signal BA
CPO becomes "1".

At this time, the human power of AND gate 103 is “1”
, “1” is input to the counter (#0) 101,
Counter (counting starts at #0HO1. When the unit processor unit (EPU) 1 issues a memory access request next, the output of the AND gate 103 becomes "1" as described above, and the counter (#0HO1 starts counting. 0HO1 resets all previous counts and starts counting again.

If a memory access request is not issued from the unit processor unit (EPU) 1 within a certain period of time, the count value in the counter (#0HO1 becomes a certain value or more, and the overflow signal 0VERO becomes “1”. This signal By becoming “1”, the unit processor unit (
The EPU (EPU) 1 is recognized as having entered a stall state, and the diagnostic processor (DGP) 6 is notified.

Similarly to the above-described operation, the crowd processor (IOP) 2 is recognized to be in a stall state when the overflow signal 0VER1 becomes "1".

〔Effect of the invention〕

As explained above, according to the present invention, it is noted that a memory access request from a processing device always occurs within a certain machine cycle, and if a memory access request is not issued within a very short certain period of time, a stall occurs. By recognizing that the stall condition is a stall condition, it is possible to detect the stall condition at an early stage, and it becomes possible to improve system processing efficiency. Furthermore, when a stall is detected, the state of the stall can be seen from a hardware tracer or the like, and furthermore, by providing the stall detection section outside the processing device, the stall detection ability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a stall detection circuit according to an embodiment of the present invention. 1... Unit processor unit (EPU), 2...
- Input/output processor (IOP), 3... Main memory unit (MMU), 4... System control unit (SCU), 5... System bus, 6... Diagnostic processor (DGP), 10...・Stall detection circuit,
101.102...Counter, 103.104...
And gate.

Claims (1)

[Scope of Claims] 1. In an information processing device in which at least one main storage device and one or more processing devices are connected to one system bus, for each of the processing devices, corresponding to the main storage device, Means for counting machine cycles or signals corresponding to machine cycles from the time when an access request is issued from the processing device to the main storage device, and a stall state when the counting means exceeds a certain value. What is claimed is: 1. An information processing device comprising: a stall detection circuit including means for recognizing.