JPH0226415A - Counter circuit - Google Patents

Abstract

PURPOSE:To simplify circuit structure and to minimize area when made into an IC by setting the number of counts by the capacity ratio of first and second capacitors, a circuit power source voltage and a reference voltage and making a voltage comparator output into a counter output. CONSTITUTION:A first capacitor 1 of small capacity is charged with a circuit power source voltage VDD in the 'H' period of a clock pulse CL, a second capacitor 2 of large capacity is charged with the charge of the first capacitor 1 in the 'L' period of the clock pulse CL, it is decided by a voltage comparator 9 whether an end-to-end voltage VC2 of the second capacitor 2 is larger than a reference voltage Vref and the output of the voltage comparator 9 is made into the counter output. Thus, compared with the case where a flip-flop is used as before, the circuit structure becomes simpler and the area when made into the IC can be made smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter circuit used in a digital circuit.

[Prior Art] Conventionally, this type of counter circuit used in digital circuits is formed using cascade-connected master-slave type flip-flop circuits FF1 to FFn, as shown in FIG. flip-flop FF,,FF
The output Q of 2...... is sent to the next stage flip-flora 1FF2. Input to the clock terminal T of FF3......, the first stage flip-flop FF,
The output obtained by performing a NAND operation on the clock pulse CL and the output Q of the n-th flip-flop FFn by a NAND circuit NA is input to the clock terminal T of the circuit.

Now, the reset terminals π of each flip-flop 1FF and ~FFn are connected in parallel, and when the reset signal RE input to the reset input terminals T and l is "L", all the flip-flops FF and ~FFn are reset. and the output terminal TO is "L". On the other hand, when the reset terminal R becomes "H", when 26 clock pulses CL input to the clock input terminal Tc are counted,
The output terminal To becomes "H" and the counting operation ends.

[Problem to be Solved by the Invention] However, in the above-mentioned conventional example, flip-flops FF l"=F ”), the counter circuit was constructed by transmitting the counter circuit, so as the number of counts increased, it was necessary to use a correspondingly large number of flip-flops FF, ~FFn, which made the circuit configuration complex and required the use of an IC. In addition, in order to realize a count number other than 26, it is necessary to add a feedback circuit, which makes the circuit configuration more complicated and makes it difficult to change the count number. The problem was that it was not easy to do.

The present invention has been made in view of the above points, and its purpose is to simplify the circuit configuration, reduce the area when integrated into an IC, and easily set an arbitrary number of counts. The object of the present invention is to provide a counter circuit that can be realized.

[Means for Solving the Problems] The counter circuit of the present invention has a counter circuit that is charged with a circuit power supply voltage via a charging control switch element that is turned on during the "H" period of a clock pulse applied to a clock input terminal. A first capacitor with a large capacity, a second capacitor with a large capacity that is charged by the electric charge of the first capacitor via a charge transfer switching element that is turned on during the "off" period of the clock pulse, and a voltage across the second capacitor. It consists of a voltage comparator that determines whether the voltage has become larger than the reference voltage.
1st. The count number is set based on the capacitance ratio of the second capacitor, the circuit power supply voltage, and the reference voltage, and the voltage comparator output is used as the counter output.

[Function] The present invention is configured as described above, and the first capacitor with a small capacity is charged with the circuit power supply voltage during the "H" period of the clock pulse, and the second capacitor with a large capacity is charged with the circuit power supply voltage during the "H" period of the clock pulse. The first capacitor is charged during the "L" period of , and the voltage comparator determines whether the voltage across the second capacitor has become greater than the reference voltage, and the output of the voltage comparator is used as the counter output. The circuit configuration is simpler than that using flip-flops.
The area when integrated into an IC can be reduced, and
1st. Since the count number can be set based on the capacitance ratio of the second capacitor, the circuit power supply voltage, and the reference voltage, any desired count number can be easily achieved.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which a charge control switch element 5 made of a pMOS transistor is turned on during the "H" period of the clock pulse CL applied to the clock input terminal Tc. ■ Circuit power supply voltage. . a first capacitor 1 of small capacity charged by the clock pulse CL;
a large-capacity second capacitor 2 that is charged with the charge of the first capacitor 1 via a charge transfer switch element 4 made of a transistor (9MO3), which is turned on during the "L" period of 9MO3);
The voltage Vc2 across the second capacitor 2 is the reference voltage Vref
It consists of a voltage comparator that determines whether the voltage has become larger than 1. 1st. Capacity ratio of second capacitors 1 and 2 and circuit power supply voltage V. lll, reference voltage V r e f
The count number 2'' is set by the reset signal R applied to the reset input terminal T8 in the embodiment.
In order to enable arbitrary reset at E, a discharge switching element 3 consisting of a NAND circuit 8, an inverter circuit n7 and an nMO3) transistor is provided, and when the reset signal RE is "L", the clock pulse CL is In addition to blocking the input, the discharging switch element 3 is turned on to discharge the charge in the second capacitor 2. The charge control switch element 5 is controlled by a clock pulse CL inverted by an inverter 6, the charge transfer switch element 4 is controlled by a clock pulse CL, and both switch elements 4 and 5 are turned on and off alternately. It is now possible to do so.

The operation of the embodiment will be described below. Now, when the reset signal RE input to the reset terminal Tll is "L", the output of the NAND circuit 8 becomes "H", the charge control switch element 5 is turned on, and the charge transfer switch element 4 is turned off. The first capacitor 1 is charged to the circuit power supply voltage VDD.

At this time, since the discharge switch element 3 is turned on at the same time and the charge of the second capacitor 2 is discharged, the voltage across the second capacitor 2 input to the non-inverting input terminal of the voltage comparator 9 is V C2 (= O) is the inverting input terminal voltage Vre
It becomes lower than f, and the voltage comparator 9 output becomes "Yes",
Even if the clock pulse CL is input, no counter output is obtained.

Next, when the reset signal RE becomes H'', the discharging switch element 3 is turned off, and the output of the NAND circuit 8 is inverted in accordance with the clock pulse CL, and the charging control switch element 5 and the charge transfer switch element 4 are inverted. is turned on and off alternately, the second capacitor 2 is gradually charged, and the counter operation is started.At this point, the clock pulse CL is "
In the case of "L", the charge control switch element 5 is turned on, the charge transfer switch element 4 is turned off, and the first capacitor 1 is charged to the power supply voltage. When it becomes "H", the charge control switch element 5 is turned off, and the charge transfer switch element 4 is turned on, so that the charge in the first capacitor 1 is transferred to the second capacitor 2 via the charge transfer switch element 4. Ru.

Here, in the initial state, the first capacitor 1 is charged by the circuit power supply voltage VDD, and the charge in the second capacitor 2 is discharged by turning on the discharging switch element 3, so that the voltage across the first capacitor 1 is V c + (0) and the voltage across the second capacitor 2, V C2 (0), is v c + (o) = Vo.

V C2 (0) = 0 It becomes.

Next, the voltage across both capacitors 1.2 when the clock pulse CL first becomes “H” VC+(t), VO2
(1) is V c , (1) = V C2 (1) = (C+/
(C++C2)) Van. However, C,, C, is
1st. This is the capacity of the second capacitors 1 and 2.

Next, when the tarok pulse CL becomes "L", the charge control switch element 5 is turned on and the first capacitor 1 reaches the circuit power supply voltage (2). Although the second capacitor 2 is charged to zero, since the charge transfer switching element 4 is off, the charge of the second capacitor 2 is conserved, and the voltage across the second capacitor 2 is c2(1).

Next, when the clock pulse CL becomes "H" and the charge transfer switch element 4 is turned on, the charge of the first capacitor 1 is transferred to the second capacitor 2 again, and the voltage across both capacitors 1.2 at this time is VC+ (2), VO2 (2
) is V c + (2) = V C2 (2) Therefore,
When the clock pulse CL becomes "H" N times, the voltage across both capacitors 1.2 becomes VC.

(N), Vcz(N) are as follows: Vc1(N) = Vc2(N)=11-
(x＞'l vo.

However, X=C2/(C++C2).

Here, when the voltage V C2 (N) across the second capacitor 2 becomes the reference voltage Vref when the tarok pulse CL becomes "H" N times, the output of the voltage comparator 9 is inverted and becomes "H". Therefore, a counter output indicating that the clock pulse CL has been counted N times is obtained.
The count number N is determined by the following formula.

In addition, C+ = I PF , C2 = 9 p F
, V r e f2.6V, V, , when it is set as 5V, N=6.

As described above, in the present invention, the first capacitor 1 of small capacity is connected to the circuit power supply voltage ■ during the "H" period of the clock pulse CL. .

The large-capacity second capacitor 2 is charged with the electric charge of the first capacitor 1 during the "L" period of the clock pulse CL, and the voltage across the second capacitor 2 is V C2 (N
) is larger than the reference voltage Vref by the voltage comparator 9, and the output of the voltage comparator 9 is used as the counter output. This means that the circuit configuration is simpler than when it is formed using an integrated circuit, and the area when integrated into an IC can be reduced. Also, 1st. Capacity ratio of second capacitors 1 and 2 and circuit power supply voltage■. . , reference voltage Vref
Since the count number N can be set by , it is possible to easily realize an arbitrary count number N. Furthermore, the first. Since the count number N is set according to the capacitance ratio of the second capacitors 1 and 2, it is possible to reduce the variation error when integrated into an IC.

[Effects of the Invention] The present invention is configured as described above, and the first capacitor with a small capacity is charged with the circuit power supply voltage during the "H" period of the clock pulse, and the second capacitor with a large capacity is charged with the circuit power supply voltage during the "H" period of the clock pulse. Charge the first capacitor during the 'L' period of the pulse, use a voltage comparator to determine whether the voltage across the second capacitor has become greater than the reference voltage, and use the voltage comparator output as the counter output. The circuit configuration is simpler than that using flip-flops.
The area when integrated into an IC can be reduced, and
1st. Since the count number can be set based on the capacitance ratio of the second capacitor, the circuit power supply voltage, and the reference voltage, there is an effect that an arbitrary count number can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1 is a first capacitor, 2 is a second capacitor, 3 is a discharging switch element, 4 is a charge transfer switch element, 5 is a charging control switch element, and 9 is a voltage comparator. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] (1) A small-capacity first capacitor that is charged with the circuit power supply voltage via a charging control switch element that is turned on during the "H" period of the clock pulse applied to the clock input terminal; A large-capacity second capacitor that is charged with the charge of the first capacitor through a charge transfer switch element that is turned on during the period, and a voltage that determines whether the voltage across the second capacitor has become larger than the reference voltage. 1. A counter circuit comprising: a comparator; the count number is set based on the capacitance ratio of the first and second capacitors, the circuit power supply voltage, and the reference voltage; and the output of the voltage comparator is used as the counter output.