JPH02276270A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02276270A JPH02276270A JP1097777A JP9777789A JPH02276270A JP H02276270 A JPH02276270 A JP H02276270A JP 1097777 A JP1097777 A JP 1097777A JP 9777789 A JP9777789 A JP 9777789A JP H02276270 A JPH02276270 A JP H02276270A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- film
- polycrystalline silicon
- silicon film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 14
- 238000001259 photo etching Methods 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の抵抗素子構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resistive element structure of a semiconductor device.
ＬＳＩの集積度の向上につれて、多結晶シリコン抵抗技
術の重要性がますます高くなってきている。例えば、高
抵抗負荷型スタチックＲＡＭの場合、非常に高い抵抗値
を持つ抵抗素子が必要である。As the degree of integration of LSIs increases, polycrystalline silicon resistor technology is becoming increasingly important. For example, in the case of a high resistance load type static RAM, a resistance element with a very high resistance value is required.
従来の半導体装置の抵抗素子構造は、第２図の様であっ
た。すなわち、半導体基板１上に第１絶縁膜２が形成さ
れており、その上に真性多結晶シリコン膜からなる抵抗
体３と、それに接続した不純物を導入した多結晶シリコ
ン膜からなる配線４とで構成されていた。The structure of a resistive element in a conventional semiconductor device is as shown in FIG. That is, a first insulating film 2 is formed on a semiconductor substrate 1, on which a resistor 3 made of an intrinsic polycrystalline silicon film, and a wiring 4 made of a polycrystalline silicon film into which impurities are introduced are connected to the resistor 3. It was configured.
この事を工程を追って説明していく。まず第４図（ａ）
の如く、半導体基板１上に絶縁膜として第１シリコン酸
化１１１５を化学気相成長法などで例えば２０００（Ａ
）以上形成する。そして前記第１シリコン酸化膜５上に
多結晶シリコン膜６を１０００（Ａ）形成する。一般に
化学気相成長法により６２０（’Ｃ）でシランガスの化
学反応により堆積させる。I will explain this step by step. First, Figure 4(a)
As shown in FIG.
) or more. Then, a polycrystalline silicon film 6 having a thickness of 1000 (A) is formed on the first silicon oxide film 5. It is generally deposited by chemical vapor deposition at 620 ('C) by chemical reaction of silane gas.
次に第４図（ｂ）の如く、前記多結晶シリコン膜６の高
抵抗にしたい部分の上にレジストマスク７を形成する。Next, as shown in FIG. 4(b), a resist mask 7 is formed on the portion of the polycrystalline silicon film 6 that is desired to have a high resistance.
そしてそれ以外の部分すなわち配線領域４を形成するた
めに、リンや砒素やほう素などの不純物注入８を行なう
。たとえばリンのイオン打ち込み法の場合、エネルギー
３０（Ｋｅｙ）、ドーズ量５Ｘ１０１５（ｃｍ−２）な
どが適当であろう。Then, in order to form other parts, that is, wiring regions 4, impurity implantation 8 of phosphorus, arsenic, boron, etc. is performed. For example, in the case of phosphorus ion implantation, an energy of 30 (key) and a dose of 5×10 15 (cm −2 ) may be appropriate.
次に第４図（Ｃ）の如く、前記レジストマスク７を除去
し、抵抗素子として余分な部分を、フォトエツチングの
工程により取り除く。Next, as shown in FIG. 4(C), the resist mask 7 is removed, and the excess portion as a resistor element is removed by a photo-etching process.
次に第４図（ｄ）の如く、他の素子と分離するために、
絶縁膜として第２シリコン酸化膜９を形成する。化学気
相成長法で１０００ （人）以上の膜厚にする。その後
、他の素子と接続するために、フォトエツチングの工程
により前記第２シリコン酸化膜９にコンタクトホールを
形成する。そして他の素子との配線として、アルミニウ
ム膜１０をスパッタ法により形成し、フォト・エツチン
グの工程により余分な部分を取り除く。以上の工程によ
り従来技術の抵抗素子が完成する。Next, as shown in FIG. 4(d), in order to separate it from other elements,
A second silicon oxide film 9 is formed as an insulating film. Use chemical vapor deposition to create a film with a thickness of 1,000 or more. Thereafter, contact holes are formed in the second silicon oxide film 9 by a photoetching process in order to connect to other elements. Then, as wiring with other elements, an aluminum film 10 is formed by sputtering, and excess portions are removed by a photo-etching process. Through the above steps, a conventional resistance element is completed.
しかし、前述の従来技術では、微細化が不可能という問
題点を有する。However, the above-mentioned conventional technology has the problem that miniaturization is impossible.
第２８回半導体専門講習会予稿集、Ｐ６９〜１１４、ｒ
ｃＭＯ３争ＳＲＡＭプロセスデバイス技術、酒井芳男著
」にもある様に、前記抵抗体２０３の寸法を短かくする
と、急激に抵抗値が低下し、予定の抵抗値を確保するこ
とが困難になる。したがって、ある−窓以上の寸法（現
在では約３（μｍ）以上）が必要であり、微細化の大き
な障壁となっていた。Proceedings of the 28th Semiconductor Specialized Seminar, P69-114, r
As stated in ``CMO3 Competition SRAM Process Device Technology'' by Yoshio Sakai, if the dimensions of the resistor 203 are shortened, the resistance value will drop rapidly and it will be difficult to secure the expected resistance value. Therefore, a size larger than a certain window (currently about 3 (μm) or larger) is required, which has been a major barrier to miniaturization.
そこで本発明は、このような問題点を解決するもので、
その目的とするところは、短かい抵抗素子長で、高い抵
抗値を確保する抵抗素子構造を提供するところにある。Therefore, the present invention aims to solve these problems.
The objective is to provide a resistive element structure that ensures a high resistance value with a short resistive element length.
本発明の半導体装置は、
（１）半導体基板上に絶縁膜が形成されており、前記絶
縁膜上には、多結晶シリコン膜から成る抵抗体と、該真
性多結晶シリコン膜に不純物を導入した多結晶シリコン
膜から成る配線とで構成されている抵抗素子において、
前記抵抗体の下の前記絶縁膜の下のすくなくとも一部に
、下層配線もしくは下層絶縁膜からなるパターンが形成
されており、すくなくとも１ケ所以上の前記下層配線パ
ターンもしくは前記下層絶縁膜パターンを横切る様に、
前記抵抗体が配置されていることを特徴とする。The semiconductor device of the present invention includes: (1) An insulating film is formed on a semiconductor substrate, and a resistor made of a polycrystalline silicon film is provided on the insulating film, and an impurity is introduced into the intrinsic polycrystalline silicon film. In a resistance element composed of wiring made of polycrystalline silicon film,
A pattern made of lower layer wiring or a lower layer insulating film is formed at least in a part under the insulating film under the resistor, and the pattern is such that it crosses at least one or more of the lower layer wiring pattern or the lower layer insulating film pattern. To,
It is characterized in that the resistor is arranged.
第１図は、本発明の１実施例における半導体装置の断面
図である。また第３図（ａ）〜第３図（ｄ）は、その製
造工程ごとの主要断面図である。FIG. 1 is a sectional view of a semiconductor device in one embodiment of the present invention. Moreover, FIGS. 3(a) to 3(d) are main sectional views for each manufacturing process.
なお、実施例の全図において、同一の機能を有するもの
には、同一の符号を付け、その繰り返しの説明は省略す
る。In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
以下第３図（ａ）〜第３図（ｄ）図に従がい、説明して
いく。The explanation will be given below according to FIGS. 3(a) to 3(d).
まず第３図（ａ）の如く、半導体基板１上に絶縁膜とし
て、第１シリコン酸化膜５を、化学気相成長法（以下Ｃ
ＶＤ法）により例えば、４０００（八）形成する。例え
ば、７６０ （’Ｃ）の温度で５ｉＨ２Ｃ，１７２とＮ
２０との混合ガスを供給し、気相あるいは、前記半導体
基板１表面上で化学反応させ、前記第１シリコン酸化膜
５を堆積させる。First, as shown in FIG. 3(a), a first silicon oxide film 5 is deposited as an insulating film on a semiconductor substrate 1 using a chemical vapor deposition method (hereinafter referred to as C).
For example, 4000 (8) is formed by VD method). For example, 5iH2C, 172 and N at a temperature of 760 ('C)
The first silicon oxide film 5 is deposited by supplying a mixed gas with 20 and causing a chemical reaction in the vapor phase or on the surface of the semiconductor substrate 1.
そして前記第１シリコン酸化膜５上に、第１多結晶シリ
コン膜１１を形成する。６２０（’Ｃ）でシランガスを
熱分解させ５０００（Ａ）堆積させる。Then, a first polycrystalline silicon film 11 is formed on the first silicon oxide film 5. Silane gas is thermally decomposed at 620 ('C) and deposited at 5000 (A).
５５０（”Ｃ）付近で成長させたアモルファスシリコン
膜でもよい。そして、後に形成される抵抗体の下の一部
を残して、フォト・エツチングの工程により前記第１多
結晶シリコン膜１１を除去する。An amorphous silicon film grown at around 550 ("C) may be used. Then, the first polycrystalline silicon film 11 is removed by a photo-etching process, leaving a portion under the resistor to be formed later. .
次に第３図（ｂ）の如く、ＣＶＤ法により第２シリコン
酸化膜１２を１５００（Ａ）形成する。Next, as shown in FIG. 3(b), a second silicon oxide film 12 1500 (A) is formed by the CVD method.
そして抵抗素子となる第２多結晶シリコン膜１３を、例
えば１０００（Ａ）の膜厚で、前記第１多結晶シリコン
膜１１と同様な方法で形成する。Then, a second polycrystalline silicon film 13 serving as a resistive element is formed to have a thickness of, for example, 1000 (A) in the same manner as the first polycrystalline silicon film 11.
なお膜厚は必要な抵抗値に合わせて決定する。通常この
なにも不純物を導入していない前記第２多結晶シリコン
膜１３を抵抗体９として用いる。前記第２多結晶シリコ
ン膜３０５の抵抗体にする上にレジストマスク７を形成
し、それをマスクとして配線４を形成するために、不純
物イオン打ち込みをする。砒素をエネルギー６０ＫｅＶ
、 ドーズｉｔ６ Ｘ １０１５ｃ ｍ−’などが適当
であろう。Note that the film thickness is determined according to the required resistance value. Usually, the second polycrystalline silicon film 13 into which no impurity is introduced is used as the resistor 9. A resist mask 7 is formed on the second polycrystalline silicon film 305 to be used as a resistor, and impurity ions are implanted to form the wiring 4 using the resist mask 7 as a mask. Arsenic with energy 60KeV
, dose it6 x 1015 cm-', etc. would be appropriate.
次に第３図（Ｃ）の如く、前記レジストマスク７を除去
し、抵抗素子として不要な部分をフォト・エツチングの
工程により除去する。Next, as shown in FIG. 3(C), the resist mask 7 is removed, and portions unnecessary as resistive elements are removed by a photo-etching process.
次に第１図の如く、第３シリコン酸化膜１４をＣＶＤ法
で例えば４０００（Ａ）形成する。そして不純物を活性
化するために、９５０ （℃）２０（分）はどチッ素雰
囲気中で熱処理をする。そして最後に前記第３シリコン
酸化膜１４にフォト・エツチングの工程によりコンタク
トホールを形成し、アルミニウム膜１０をスパッタ法に
より１（μｍ）形成し、不要な部分を、フォト・エツチ
ングの工程により除去し、本発明の抵抗素子が完成する
。Next, as shown in FIG. 1, a third silicon oxide film 14 having a thickness of, for example, 4000 (A) is formed by the CVD method. Then, in order to activate the impurities, heat treatment is performed at 950° C. for 20 minutes in a nitrogen atmosphere. Finally, a contact hole is formed in the third silicon oxide film 14 by a photo-etching process, an aluminum film 10 is formed with a thickness of 1 (μm) by a sputtering method, and unnecessary portions are removed by a photo-etching process. , the resistance element of the present invention is completed.
この様に、抵抗体３の下に絶縁膜を介して第１多結晶シ
リコン膜１１を形成することにより、前記抵抗体３は段
差を乗り越えていく形になる。したがって、その分だけ
平面的長さが一定にもかかわらず、抵抗体長が長くなり
、高い抵抗値が得られる。したがって平面的抵抗体長が
、３（μｍ）以下の場合でも、段差となる前記第１多結
晶シリｐン１１の膜厚を厚くすることにより、十分な抵
抗値を得ることが可能となり、集積密度の増大、しいて
は、集積回路チップ全体の微細化にもつながる。In this way, by forming the first polycrystalline silicon film 11 under the resistor 3 with an insulating film interposed therebetween, the resistor 3 is shaped to go over the step. Therefore, even though the planar length is constant, the length of the resistor becomes longer and a higher resistance value can be obtained. Therefore, even if the planar resistor length is 3 (μm) or less, by increasing the thickness of the first polycrystalline silicon 11 that forms the step, it is possible to obtain a sufficient resistance value, and the integration density can be increased. This also leads to an increase in the size of the integrated circuit chip, which in turn leads to miniaturization of the entire integrated circuit chip.
また本実施例では、段差を作るために、多結晶シリコン
を用いたが、高融点金属シリサイド膜にしたり、不純物
を多量に注入した多結晶シリコン膜なら、抵抗値が低い
ので他の素子の配線や、他の素子のゲート電極になるこ
とが可能であり、それらをかねそ、なえることもできる
。In addition, in this example, polycrystalline silicon was used to create the step, but a high melting point metal silicide film or a polycrystalline silicon film injected with a large amount of impurities has a low resistance value, so it can be used for wiring of other elements. It can also be used as a gate electrode for other devices, and can also be used as a gate electrode for other devices.
また本実施例では、抵抗体の下に段差を２ケ所形成した
が、第５図の様に１ケ所の段差でも、あるいは３ケ所以
上でも同様の効果があることは言うまでもない。Further, in this embodiment, two steps are formed under the resistor, but it goes without saying that the same effect can be obtained even with one step as shown in FIG. 5, or with three or more steps.
以上本発明者によってなされた発明を、前記実施例に基
づき、具体的に説明してきたが、本発明は、前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
において、種々変形し得ることは勿論である。Although the invention made by the present inventor has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course you can get it.
例えば、第６図の様に、２層の膜で段差を形成したり、
下層パターンを絶縁膜にしても、同様な効果を有する。For example, as shown in Figure 6, forming a step with two layers of film,
A similar effect can be obtained even if the lower layer pattern is an insulating film.
以上述べてきたｔ、ｌに、本発明の半導体装置によれば
、抵抗体の下に絶縁膜を介して下層配線もしくは下層絶
縁膜の段差を形成することにより、以下に述べる効果を
有する。すなわち、抵抗素子長を平面的に短かくしても
十分な抵抗値が得られ、しいては、集積回路全体の微細
化が可能となる。Regarding t and l described above, according to the semiconductor device of the present invention, by forming a step of the lower wiring or the lower layer insulating film under the resistor through the insulating film, the following effects can be obtained. In other words, a sufficient resistance value can be obtained even if the length of the resistor element is shortened in plan, and the entire integrated circuit can be miniaturized.
第１図は、本発明の半導体装置の一実施例を示す主要断
面図。
第２図は、従来の半導体装置を示す主要断面図。
第３図（ａ）〜第３図（ｄ）は、本発明の半導体装置の
製造方法の一例を工程順に説明するための主要断面図。
第４図（ａ）〜第４図（ｄ）は、従来の半導体装置の製
造工程毎の主要断面図。
第５図は、本発明の変形例を示す主要断面図。
第６図は、本発明の別の変形例を示す主要断面図。
１・・・半導体基板
２・・・第１絶縁膜
３・・・抵抗体
４・・・配線
５・・・第１シリコン酸化膜
６・・・多結晶シリコン膜
７・・・レジストマスク
８・・・不純物イオンビーム
９・・・第２シリコン酸化膜
１０Φ・・アルミニウム膜
１１・・・第１多結晶シリコン膜
１２ ・
１３ ・
１４ ・
１５ ・
１６ ＠
・第２シリコン酸化膜
・第２多結晶シリコン膜
・第３シリコン酸化膜
・第４シリコン酸化膜
・第５シリコン酸化膜
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部（他１名）区FIG. 1 is a main sectional view showing an embodiment of a semiconductor device of the present invention. FIG. 2 is a main cross-sectional view showing a conventional semiconductor device. FIGS. 3(a) to 3(d) are main cross-sectional views for explaining an example of the method for manufacturing a semiconductor device of the present invention in the order of steps. FIGS. 4(a) to 4(d) are main sectional views of each manufacturing process of a conventional semiconductor device. FIG. 5 is a main sectional view showing a modification of the present invention. FIG. 6 is a main sectional view showing another modification of the present invention. 1... Semiconductor substrate 2... First insulating film 3... Resistor 4... Wiring 5... First silicon oxide film 6... Polycrystalline silicon film 7... Resist mask 8. ...Impurity ion beam 9...Second silicon oxide film 10Φ...Aluminum film 11...First polycrystalline silicon film 12 ・ 13 ・ 14 ・ 15 ・ 16 @ ・Second silicon oxide film・Second polycrystalline silicon film Silicon film, 3rd silicon oxide film, 4th silicon oxide film, 5th silicon oxide film Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (and 1 other person) Ward
Claims (1)
縁膜上には、多結晶シリコン膜から成る抵抗体と、該真
性多結晶シリコン膜に不純物を導入した多結晶シリコン
膜から成る配線とで構成されている抵抗素子において、
前記抵抗体の下の前記絶縁膜の下のすくなくとも一部に
、下層配線もしくは下層絶縁膜からなるパターンが形成
されており、すくなくとも１ケ所以上の前記下層配線パ
ターンもしくは前記下層絶縁膜パターンを横切る様に、
前記抵抗体が配置されていることを特徴とする半導体装
置。(1) An insulating film is formed on a semiconductor substrate, and on the insulating film, a resistor made of a polycrystalline silicon film and a wiring made of a polycrystalline silicon film in which impurities are introduced into the intrinsic polycrystalline silicon film. In a resistive element composed of
A pattern made of lower layer wiring or a lower layer insulating film is formed at least in a part under the insulating film under the resistor, and the pattern is such that it crosses at least one or more of the lower layer wiring pattern or the lower layer insulating film pattern. To,
A semiconductor device characterized in that the resistor is arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1097777A JPH02276270A (en) | 1989-04-18 | 1989-04-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1097777A JPH02276270A (en) | 1989-04-18 | 1989-04-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02276270A true JPH02276270A (en) | 1990-11-13 |
Family
ID=14201263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1097777A Pending JPH02276270A (en) | 1989-04-18 | 1989-04-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02276270A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005303051A (en) * | 2004-04-13 | 2005-10-27 | Ricoh Co Ltd | Semiconductor device and manufacturing method thereof |
-
1989
- 1989-04-18 JP JP1097777A patent/JPH02276270A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005303051A (en) * | 2004-04-13 | 2005-10-27 | Ricoh Co Ltd | Semiconductor device and manufacturing method thereof |
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