JPH0240927A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0240927A
JPH0240927A JP63191328A JP19132888A JPH0240927A JP H0240927 A JPH0240927 A JP H0240927A JP 63191328 A JP63191328 A JP 63191328A JP 19132888 A JP19132888 A JP 19132888A JP H0240927 A JPH0240927 A JP H0240927A
Authority
JP
Japan
Prior art keywords
terminal
pad
semiconductor
semiconductor device
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63191328A
Other languages
Japanese (ja)
Inventor
Shigemitsu Nakamura
中村　重光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63191328A priority Critical patent/JPH0240927A/en
Publication of JPH0240927A publication Critical patent/JPH0240927A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07552—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/527—Multiple bond wires having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明はケースに搭載された半導体チップの接地ＧＮＤ
端子及び電源■。Ｃ端子と、ケースの周囲に設けられた
リードとのボンディング接続を改良した半導体装置に関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a grounding GND for a semiconductor chip mounted on a case.
Terminal and power supply■. The present invention relates to a semiconductor device with improved bonding connection between a C terminal and a lead provided around a case.

［従来の技術］ 従来の半導体記憶回路装置においては、第２図に示すよ
うにケース１の周縁部にリード２が設けられており、ケ
ース１に搭載された半導体チップ３上のパッド４．４ａ
、４ｂと各リード２とは夫々ワイヤ５．５ａ、５ｂによ
りボンディング接続されている。[Prior Art] In a conventional semiconductor memory circuit device, as shown in FIG.
, 4b and each lead 2 are bonded to each other by wires 5.5a and 5b, respectively.

リード２のうち、例えば、Ｎ［Ｌ　１乃至１１及びＮｎ
。Among the leads 2, for example, N[L 1 to 11 and Nn
.

１３乃至２３（Ｎａは図の周囲に記載）のリードは信号
端子用のものであり、阻１２のリードはＧＮＤ端子用、
Ｎｕ、　２４のリードは■ｃｏ端子用のものである。Leads 13 to 23 (Na is written around the figure) are for signal terminals, lead 12 is for GND terminal,
Leads Nu and 24 are for the ■co terminal.

一方、半導体チップ３に設けられたパッド４は信号端子
用のものであり、パッド４ａ及び４ｂは夫々ＶＣＣ端子
用及びＧＮＤ端子用のものであって、いずれも同じ大き
さに形成されている。On the other hand, the pads 4 provided on the semiconductor chip 3 are for signal terminals, and the pads 4a and 4b are for VCC terminals and GND terminals, respectively, and are formed to have the same size.

而して、ＧＮＤ端子及びＶＣＣ端子に大きな電流を流す
と、ボンディングワイヤが切断されてしまうため、ＶＣ
Ｃ端子用のパッド４ａとリード２（Ｎ［Ｌ２４）とを接
続するワイヤ５ａ及びＧＮＤ端子用のパッド４ｂとリー
ド２（Ｎ［ｉ、１２）を接続するワイヤ５ｂとしては、
複数本のワイヤを束ねた東線か、又は線径が太いワイヤ
を使用している。Therefore, if a large current is applied to the GND terminal and the VCC terminal, the bonding wire will be cut, so the VC
The wire 5a connecting the pad 4a for the C terminal and the lead 2 (N[L24) and the wire 5b connecting the pad 4b for the GND terminal and the lead 2 (N[i, 12) are as follows.
East wire, which is a bundle of multiple wires, or wire with a thick wire diameter is used.

［発明が解決しようとする課題］ しかしながら、この従来の半導体装置においては、ＶＣ
Ｃ端子及びＧＮＤ端子用のワイヤ５ａ、５ｂが複数本の
素線からなる東線か、又は大径のワイヤであったため、
ボンディングされた状態でパッド４ａ、４ｂに無理な力
が加わりやすく、このような力が加わるとチップ３が破
損してしまうという欠点がある。[Problem to be solved by the invention] However, in this conventional semiconductor device, the VC
Because the wires 5a and 5b for the C terminal and GND terminal were east wires made of multiple strands or large diameter wires,
There is a disadvantage that unreasonable force is likely to be applied to the pads 4a and 4b in the bonded state, and the chip 3 will be damaged if such force is applied.

本発明はかかる問題点に鑑みてなされたものであって、
ワイヤボンディング接合部を強化することができ、半導
体チップの破損を防止することができる半導体装置を提
供することを目的とする。The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor device that can strengthen wire bonding joints and prevent damage to semiconductor chips.

［課題を解決するための手段］ 本発明に係る半導体装置は、ケースに搭載された半導体
チップの接地ＧＮＤ端子及び電源■。。端子用のパッド
サイズが、半導体の電流容量に応じて、他の信号端子の
パッドサイズより大きいことを特徴とする。[Means for Solving the Problems] A semiconductor device according to the present invention has a ground GND terminal and a power supply (1) of a semiconductor chip mounted on a case. . It is characterized in that the pad size for the terminal is larger than the pad size for other signal terminals, depending on the current capacity of the semiconductor.

［作用］ 本発明においては、パッドサイズが接地ＧＮＤ端子及び
電源ＶＣＣ端子用のものと、他の信号端子用のものとで
異なる。[Function] In the present invention, pad sizes are different between those for the ground GND terminal and the power supply VCC terminal and those for other signal terminals.

即ち、ＧＮＤ−Ｖｃｃ端子用パッドは信号端子用パッド
よりも半導体の電流容量に応じて大きく形成されている
。これにより、ＧＮＤ−Ｖｃｃ端子のワイヤボンディン
グ接合部が強化されるので、ＧＮＤ・ＶＣＣ端子用に大
径のボンディングワイヤを使用しても、チップが破損し
たりすることはない。That is, the GND-Vcc terminal pad is formed larger than the signal terminal pad in accordance with the current capacity of the semiconductor. As a result, the wire bonding joint of the GND-Vcc terminal is strengthened, so even if a large-diameter bonding wire is used for the GND/VCC terminal, the chip will not be damaged.

［実施例］ 次に、本発明の実施例について添付の図面を参照して説
明する。[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

第１図は本発明の実施例に係る半導体装置を示す平面図
である。第１図において、第２図と同一物には同一符号
を付しである。FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. In FIG. 1, the same parts as in FIG. 2 are given the same reference numerals.

半導体チップ３の周縁部には、その２隅部に、電源Ｖｃ
ｃ用のパッド６ａと、接地ＧＮＤ用のパッド６ｂとが設
けられている。その他の周縁部には、信号端子用の複数
個のパッド４が相互に適長間隔をおいて配列されている
。At the periphery of the semiconductor chip 3, a power supply Vc is connected at two corners.
A pad 6a for GND and a pad 6b for ground GND are provided. On the other peripheral portion, a plurality of pads 4 for signal terminals are arranged at appropriate intervals.

そして、ケース１の縁部に設けられたリード２と各パッ
ド４及びパッド６ａ、６ｂとは、夫々細径のワイヤ５及
び太径のワイヤ５ａ、５ｂによりボンディング接続され
ている。The lead 2 provided on the edge of the case 1 and each pad 4 and pads 6a and 6b are bonded and connected by a small diameter wire 5 and a large diameter wire 5a and 5b, respectively.

而して、本実施例においては、電源ＶＣＣ端子用のパッ
ド６ａと、接地ＧＮＤ端子用のパッド６ｂは、半導体の
電流容量に応じて、他の信号端子用パッド４よりも大き
く、即ち大面積に形成されている。In this embodiment, the pad 6a for the power supply VCC terminal and the pad 6b for the ground GND terminal are larger than the other signal terminal pads 4, that is, have a large area, depending on the current capacity of the semiconductor. is formed.

このように構成される半導体装置においては、半導体の
電流容量に応じて、ＧＮＤ・ＶＣＣ端子用のボンディン
グワイヤ５ａ、５ｂを太径のワイヤにするか又は複数本
のワイヤを束ねた東線にすると共に、その半導体チップ
３のパッド６ａ、６ｂも大きなサイズのものにしている
。このため、この接合部が強化され、このパッド６ａ、
６ｂに大径等のワイヤ５ａ、５ｂをボンディングしても
、パッド６ａ、６ｂに無理な力が加わってチップ３を破
損させてしまうということがない。このため、電流容量
が大きな半導体装置についても、チップの破損が生じる
ことがなく、確実にワイヤボンディングすることができ
る。In a semiconductor device configured in this way, depending on the current capacity of the semiconductor, the bonding wires 5a and 5b for the GND/VCC terminals are wires with a large diameter or are made into east wires made by bundling multiple wires. At the same time, the pads 6a and 6b of the semiconductor chip 3 are also made large in size. Therefore, this joint is strengthened, and this pad 6a,
Even if large diameter wires 5a, 5b are bonded to pads 6b, the chip 3 will not be damaged due to excessive force being applied to the pads 6a, 6b. Therefore, even for a semiconductor device having a large current capacity, wire bonding can be performed reliably without chip damage.

［発明の効果］ 以上説明したように、本発明によれば、半導体チップ上
の接地ＧＮＤ端子及び電源ＶＣＣ端子のパッドを半導体
の電流容量に応じて他の信号端子用パッドよりも大きく
したから、ワイヤボンディング接合部が強化され、チッ
プの破損等によるボンディング不良が回避される。この
ように本発明は半導体装置の歩留向上に著しい貢献をな
す。[Effects of the Invention] As explained above, according to the present invention, the pads for the ground GND terminal and the power supply VCC terminal on the semiconductor chip are made larger than other signal terminal pads according to the current capacity of the semiconductor. The wire bonding joint is strengthened, and bonding failures due to chip breakage and the like are avoided. In this way, the present invention makes a significant contribution to improving the yield of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例に係る半導体装置を示す平面図
、第２図は従来の半導体装置を示す平面図である。 １；ケース、２；リード、３；半導体チップ、４．４ａ
、４ｂ　；パッド、５．５ａ、５ｂ；ワイヤ、６ａ、６
ｂ；大きなパッドFIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view showing a conventional semiconductor device. 1; Case, 2; Lead, 3; Semiconductor chip, 4.4a
, 4b; pad, 5.5a, 5b; wire, 6a, 6
b; large pad

Claims (1)

【特許請求の範囲】[Claims] （１）ケースに搭載された半導体チップの接地ＧＮＤ端
子及び電源Ｖｃｃ端子用のパッドサイズが、半導体の電
流容量に応じて、他の信号端子のパッドサイズより大き
いことを特徴とする半導体装置。(1) A semiconductor device characterized in that pad sizes for a ground GND terminal and a power supply Vcc terminal of a semiconductor chip mounted on a case are larger than pad sizes for other signal terminals, depending on the current capacity of the semiconductor.
JP63191328A 1988-07-30 1988-07-30 Semiconductor device Pending JPH0240927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63191328A JPH0240927A (en) 1988-07-30 1988-07-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63191328A JPH0240927A (en) 1988-07-30 1988-07-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0240927A true JPH0240927A (en) 1990-02-09

Family

ID=16272726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63191328A Pending JPH0240927A (en) 1988-07-30 1988-07-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0240927A (en)

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