JPH0241430U - - Google Patents

Info

Publication number
JPH0241430U
JPH0241430U JP1988119029U JP11902988U JPH0241430U JP H0241430 U JPH0241430 U JP H0241430U JP 1988119029 U JP1988119029 U JP 1988119029U JP 11902988 U JP11902988 U JP 11902988U JP H0241430 U JPH0241430 U JP H0241430U
Authority
JP
Japan
Prior art keywords
power supply
substrate
wire
loop
lead frames
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988119029U
Other languages
English (en)
Other versions
JPH069508Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988119029U priority Critical patent/JPH069508Y2/ja
Publication of JPH0241430U publication Critical patent/JPH0241430U/ja
Application granted granted Critical
Publication of JPH069508Y2 publication Critical patent/JPH069508Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例に係るパツケージの平
面図。第２図はキヤツプで封止した状態の縦断面
図。第３図は従来のサークアツドパツケージの平
面図。第４図は多層セラミツクパツケージで各層
ごとに電源面を設けたものの例を示す縦断面図。
第５図は本考案の他の実施例に係るパツケージの
平面図。 １…ＥＣＬ素子、２…リードフレーム、３…基
板、４…封止ガラス、５…アルミワイヤ、６…ル
ープ状電源メタライズ線、７…素子搭載部、８…
セラミツクキヤツプ、、９…メタライズ層、２０
…セラミツク枠、ＶＥＥ，ＶＢＢ，ＶＣＣ…電源
、Ｅ，Ｂ，Ｃ…各電源につながるリードフレーム
。

Claims (1)

    【実用新案登録請求の範囲】
  1. Ｎを３以上の整数、ｎを２以上の整数とし、Ｎ
    種類の電源を必要としひとつの電源について各辺
    ごとにｎ以上の電極を有する正方形の素子を収容
    するためのパツケージであつて、正方形状の、セ
    ラミツク或は金属板上に絶縁層を形成した基板３
    と、基板３の四辺外縁部に塗布された封止ガラス
    ４と、基板３の中央の素子１を搭載すべき素子搭
    載部７の四周であつて、封止ガラス４の内端に取
    り付けられる正方形のセラミツク枠２０と枠２０
    の上に設けられるＮ本のループ状電源メタライズ
    線６と、封止ガラス４によつて内方端部が固定さ
    れた多数のリードフレーム２とよりなり、リード
    フレーム２のうち最外方にある適数本のリードフ
    レームが前記Ｎ本のループ状電源メラタイズ線６
    とワイヤ５で結線され、素子１の各辺上のｎ個の
    電源電極はその直近のループ状電源メタライズ線
    ６とワイヤ５で結線されるようにした事を特徴と
    する多電源素子用パツケージ。
JP1988119029U 1988-09-09 1988-09-09 多電源素子用パツケージ Expired - Lifetime JPH069508Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988119029U JPH069508Y2 (ja) 1988-09-09 1988-09-09 多電源素子用パツケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988119029U JPH069508Y2 (ja) 1988-09-09 1988-09-09 多電源素子用パツケージ

Publications (2)

Publication Number Publication Date
JPH0241430U true JPH0241430U (ja) 1990-03-22
JPH069508Y2 JPH069508Y2 (ja) 1994-03-09

Family

ID=31363903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988119029U Expired - Lifetime JPH069508Y2 (ja) 1988-09-09 1988-09-09 多電源素子用パツケージ

Country Status (1)

Country Link
JP (1) JPH069508Y2 (ja)

Also Published As

Publication number Publication date
JPH069508Y2 (ja) 1994-03-09

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