JPH0243877A - Gradation converter - Google Patents
Gradation converterInfo
- Publication number
- JPH0243877A JPH0243877A JP19511788A JP19511788A JPH0243877A JP H0243877 A JPH0243877 A JP H0243877A JP 19511788 A JP19511788 A JP 19511788A JP 19511788 A JP19511788 A JP 19511788A JP H0243877 A JPH0243877 A JP H0243877A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- conversion
- gradation conversion
- table memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 62
- 230000004044 response Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
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- Studio Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は階調変換装置、特に、テレビカメラの映像出力
信号の階調変換を行う階調変換装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gradation conversion device, and particularly to a gradation conversion device that performs gradation conversion of a video output signal of a television camera.
従来の階調変換装置としては、階調変換のテーブルメモ
リを使ったものがある。As a conventional gradation conversion device, there is one that uses a gradation conversion table memory.
次に従来の階調変換装置について図面を参照して詳細に
説明する。Next, a conventional gradation conversion device will be described in detail with reference to the drawings.
第2図は従来の一例を示すブロック図である。FIG. 2 is a block diagram showing a conventional example.
第2図に示す階調変換装置は、A−D変換回路21と、
A−D変換回路21のディジタル信号S21から、階調
変換信号S22を出力する変換テーブルメモリ回路22
と、A−D変換回路21と、変換テーブルメモリ回路2
2にA−D変換やテーブルメモリの読出しタイミング制
御信号S23を出力するタイミング制御回路23とを含
んで構成される。The gradation conversion device shown in FIG. 2 includes an A-D conversion circuit 21,
A conversion table memory circuit 22 that outputs a gradation conversion signal S22 from the digital signal S21 of the A-D conversion circuit 21
, A-D conversion circuit 21 , and conversion table memory circuit 2
2 and a timing control circuit 23 that outputs an A-D conversion and table memory read timing control signal S23.
ここで映像信号はA−D変換回路21で8ビットのディ
ジタル信号S21に変換され、変換テーブルメモリ回路
22に出力される。Here, the video signal is converted into an 8-bit digital signal S21 by the A-D conversion circuit 21 and output to the conversion table memory circuit 22.
変換テーブルメモリ回路22はディジタル信号S21を
アドレスとするメモリ回路で、ディジタル信号の大きさ
に応じて出力される階調変換信号S22の値を記憶して
いる。変換テーブルメモリ回路22はディジタル信号S
21の階調に応じた変換値を記憶しておき、それを入力
信号に応じて順次読出すことにより、階調変換を行うこ
とができる。The conversion table memory circuit 22 is a memory circuit whose address is the digital signal S21, and stores the value of the gradation conversion signal S22 output according to the magnitude of the digital signal. The conversion table memory circuit 22 receives the digital signal S.
By storing conversion values corresponding to 21 gradations and sequentially reading them in accordance with input signals, gradation conversion can be performed.
上述した従来の階調変換装置は、映像信号をディジタル
化したあとで階調変換を行っているので、階調変換後の
信号の信号対ノイズレベル比(以後S/Nという)が向
上しないという欠点があった。The conventional gradation conversion device described above performs gradation conversion after digitizing the video signal, so the signal-to-noise level ratio (hereinafter referred to as S/N) of the signal after gradation conversion does not improve. There were drawbacks.
本発明の階調変換装置は、映像信号をディジタル化しデ
ィジタル信号を出力するA−D変換回路と、前記ディジ
タル信号にもとづいて倍率信号を出力する変換テーブル
メモリ回路と、前記倍率信号と前記映像信号にもとづい
て階調変換信号を出力するアナログ乗算回路と、前記映
像信号にもとづいて前記A−D変換回路および変換テー
ブルメモリ回路にタイミング信号を出力するタイミング
制御回路とを含んで構成される。The gradation conversion device of the present invention includes: an A-D conversion circuit that digitizes a video signal and outputs the digital signal; a conversion table memory circuit that outputs a magnification signal based on the digital signal; The device includes an analog multiplier circuit that outputs a gradation conversion signal based on the video signal, and a timing control circuit that outputs a timing signal to the A-D conversion circuit and conversion table memory circuit based on the video signal.
次に、本発明の実施例について、図面を参照して詳細に
説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
以下動作を詳細に説明する。The operation will be explained in detail below.
映像信号S10はアナログ乗算回路11およびA−D変
換回路12およびタイミング制御回路14に入力される
。The video signal S10 is input to an analog multiplication circuit 11, an A-D conversion circuit 12, and a timing control circuit 14.
A−D変換回路12は、映像信号S10を8ビツトにデ
ィジタル化し、ディジタル信号S12を出力する。ディ
ジタル信号S12は変換テーブルメモリ回路13に入力
され、倍率信号Sllに変換される。ここで倍率信号S
llは、アナログ乗算回路11で、映像信号SIOの乗
数となるものであり、変換テーブルメモリ回路13に、
ディジタル信号S12の値に応じた階調変換用乗数とし
てあらかじめ記憶しである。The A/D conversion circuit 12 digitizes the video signal S10 into 8 bits and outputs a digital signal S12. The digital signal S12 is input to the conversion table memory circuit 13 and converted into a magnification signal Sll. Here, the magnification signal S
ll is an analog multiplication circuit 11 that serves as a multiplier for the video signal SIO;
This is stored in advance as a gradation conversion multiplier corresponding to the value of the digital signal S12.
そして、変換テーブルメモリ回路13では、メモリから
読出した階調変換用乗数をアナログ信号に変換し、倍率
信号Sllとして出力する。Then, the conversion table memory circuit 13 converts the gradation conversion multiplier read from the memory into an analog signal and outputs it as a magnification signal Sll.
アナログ乗算回路12は、映像信号S10と、倍率信号
Sllの乗算を行い、階調変換信号813として出力す
る。The analog multiplication circuit 12 multiplies the video signal S10 and the magnification signal Sll, and outputs the result as a gradation conversion signal 813.
タイミング制御回路14は、A−D変換回路12のA−
D変換タイミングや変換テーブルメモリ回路13のメモ
リアクセスや読出しのためのタイミング信号S14を出
力する。The timing control circuit 14 is connected to the A-D converter circuit 12.
It outputs a timing signal S14 for D conversion timing and memory access and reading of the conversion table memory circuit 13.
本発明の階調変換装置は、ディジタル化したあとに階調
変換する代りに、アナログ信号の状態で階調変換するこ
とにより映像信号の有効な情報をそこなわずに画像のS
/Nを向上できるという優れた効果を有する。The gradation conversion device of the present invention performs gradation conversion in the analog signal state instead of converting the gradation after digitization.
It has an excellent effect of improving /N.
11・・・アナログ乗算回路、12・・・A−D変換回
路、13・・・変換テーブルメモリ回路、14・・・タ
イミング制御回路、21・・・A−D変換回路、22・
・・変換テーブルメモリ回路、23・・・タイミング制
御回路、
SIO・・・映像信号、Sll・・・倍率信号、S12
・・・ディジタル信号、313・・・階調変換信号、S
14・・・タイミング制御信号、S21・・・ディジタ
ル信号、S22・・・階調変換信号、32B・・・タイ
ミング制御信号。DESCRIPTION OF SYMBOLS 11... Analog multiplication circuit, 12... AD conversion circuit, 13... Conversion table memory circuit, 14... Timing control circuit, 21... AD conversion circuit, 22.
...Conversion table memory circuit, 23...Timing control circuit, SIO...Video signal, Sll...Magnification signal, S12
... Digital signal, 313 ... Gradation conversion signal, S
14... Timing control signal, S21... Digital signal, S22... Gradation conversion signal, 32B... Timing control signal.
Claims (1)
−D変換回路と、前記ディジタル信号にもとづいて倍率
信号を出力する変換テーブルメモリ回路と、前記倍率信
号と前記映像信号にもとづいて階調変換信号を出力する
アナログ乗算回路と、前記映像信号にもとづいて前記A
−D変換回路および変換テーブルメモリ回路にタイミン
グ信号を出力するタイミング制御回路とを含むことを特
徴とする階調変換装置。A that digitizes the video signal and outputs the digital signal
- a D conversion circuit, a conversion table memory circuit that outputs a magnification signal based on the digital signal, an analog multiplication circuit that outputs a gradation conversion signal based on the magnification signal and the video signal, and an analog multiplication circuit that outputs a gradation conversion signal based on the video signal; The above A
- A gradation conversion device comprising: a D conversion circuit; and a timing control circuit that outputs a timing signal to a conversion table memory circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19511788A JPH0243877A (en) | 1988-08-03 | 1988-08-03 | Gradation converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19511788A JPH0243877A (en) | 1988-08-03 | 1988-08-03 | Gradation converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0243877A true JPH0243877A (en) | 1990-02-14 |
Family
ID=16335778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19511788A Pending JPH0243877A (en) | 1988-08-03 | 1988-08-03 | Gradation converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0243877A (en) |
-
1988
- 1988-08-03 JP JP19511788A patent/JPH0243877A/en active Pending
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