JPH0270436U - - Google Patents

Info

Publication number
JPH0270436U
JPH0270436U JP1988150470U JP15047088U JPH0270436U JP H0270436 U JPH0270436 U JP H0270436U JP 1988150470 U JP1988150470 U JP 1988150470U JP 15047088 U JP15047088 U JP 15047088U JP H0270436 U JPH0270436 U JP H0270436U
Authority
JP
Japan
Prior art keywords
semiconductor element
electrode
center
portion facing
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988150470U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988150470U priority Critical patent/JPH0270436U/ja
Publication of JPH0270436U publication Critical patent/JPH0270436U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は、本考案による半導体素子の実装方式
を示す斜視図、第２図は従来の半導体素子の実装
方式を示す斜視図である。第３図ａ〜ｃは、本考
案による半導体素子の実装方式による実装メカニ
ズムを示す断面模式図である。 １……配線基板、２……配線パターン、３……
樹脂、４……金属突起、５……電極パツド、６…
…半導体素子、７……異方性導電膜、８……導電
粒子、９……樹脂の凸部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 電極上に金属突起を有する半導体素子と、前記
    電極と相対する配線パターンとの間に載置され、
    前記半導体素子の中心部に相対する部分が前記半
    導体素子の中心部以外に相対する部分よりも厚い
    シート状樹脂によつて、前記半導体素子と前記基
    板とがフエースダウンにて実装されていることを
    特徴とする半導体素子。
JP1988150470U 1988-11-18 1988-11-18 Pending JPH0270436U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988150470U JPH0270436U (ja) 1988-11-18 1988-11-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988150470U JPH0270436U (ja) 1988-11-18 1988-11-18

Publications (1)

Publication Number Publication Date
JPH0270436U true JPH0270436U (ja) 1990-05-29

Family

ID=31423646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988150470U Pending JPH0270436U (ja) 1988-11-18 1988-11-18

Country Status (1)

Country Link
JP (1) JPH0270436U (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008120564A1 (ja) * 2007-03-28 2008-10-09 Nec Corporation 電子部品の実装構造、及び電子部品の実装方法
JP2010514188A (ja) * 2006-12-21 2010-04-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ キャリア、及びキャリアに基づく光半導体デバイス
JP2011029516A (ja) * 2009-07-28 2011-02-10 Shinko Electric Ind Co Ltd 電子部品装置の製造方法及び治具
JP2014103176A (ja) * 2012-11-16 2014-06-05 Shin Etsu Chem Co Ltd 支持基材付封止材、封止後半導体素子搭載基板、封止後半導体素子形成ウエハ、半導体装置、及び半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010514188A (ja) * 2006-12-21 2010-04-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ キャリア、及びキャリアに基づく光半導体デバイス
TWI469392B (zh) * 2006-12-21 2015-01-11 皇家飛利浦電子股份有限公司 載體及基於此載體之光學半導體裝置
WO2008120564A1 (ja) * 2007-03-28 2008-10-09 Nec Corporation 電子部品の実装構造、及び電子部品の実装方法
JPWO2008120564A1 (ja) * 2007-03-28 2010-07-15 日本電気株式会社 電子部品の実装構造、及び電子部品の実装方法
JP2011029516A (ja) * 2009-07-28 2011-02-10 Shinko Electric Ind Co Ltd 電子部品装置の製造方法及び治具
JP2014103176A (ja) * 2012-11-16 2014-06-05 Shin Etsu Chem Co Ltd 支持基材付封止材、封止後半導体素子搭載基板、封止後半導体素子形成ウエハ、半導体装置、及び半導体装置の製造方法

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