JPH0284952U - - Google Patents

Info

Publication number
JPH0284952U
JPH0284952U JP16226088U JP16226088U JPH0284952U JP H0284952 U JPH0284952 U JP H0284952U JP 16226088 U JP16226088 U JP 16226088U JP 16226088 U JP16226088 U JP 16226088U JP H0284952 U JPH0284952 U JP H0284952U
Authority
JP
Japan
Prior art keywords
trace
addresses
target microprocessor
memory
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16226088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16226088U priority Critical patent/JPH0284952U/ja
Publication of JPH0284952U publication Critical patent/JPH0284952U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るタスクトレース回路の一
実施例を示す要部構成図、第2図はメモリマツプ
を示す図である。 1……レジスタ、2……トレースメモリ、3…
…ANDダート、4……第1のラツチ、5……第
2のラツチ、6,7,8,9……バスコンパレー
ク、10……ターゲツトマイクロプロセツサ。
FIG. 1 is a block diagram showing a main part of an embodiment of a task trace circuit according to the present invention, and FIG. 2 is a diagram showing a memory map. 1...Register, 2...Trace memory, 3...
...AND dart, 4...first latch, 5...second latch, 6,7,8,9...bus comparator, 10...target microprocessor.

Claims (1)

【実用新案登録請求の範囲】 マルチタスクが可能なターゲツトマイクロプロ
セツサが実行した命令やそのアドレス等を追跡し
てこれをトレースメモリに記録し、後でそのトレ
ース内容を読み出して適宜の処理を行なつた後C
RT表示画面に表示し解析することができるよう
に構成されたインサーキツト・エミユレータにお
いて、 ターゲツトマイクロプロセツサが実行した命令
やそのアドレス等を予め設定した値と比較し、メ
モリの特定のアドレス領域をプログラムが走行し
ているときに限りアクテイブとなる信号を発生す
る手段と、 ターゲツトマイクロプロセツサが実行した命令
やそのアドレス等を予め設定した値と比較し、メ
モリの特定のアドレス領域にある値を書き込んだ
ときに限りアクテイブとなる信号を発生する手段
と、 上記2つの手段の出力が共にアクテイブのとき
にのみターゲツトマイクロプロセツサが実行した
命令やそのアドレス等をサンプルしてトレースメ
モリに記録する手段 を具備し、注目するタスクの関数の実行のみを
トレースすることができるようにしたタスクトレ
ース回路。
[Claim for Utility Model Registration] A system that tracks instructions and their addresses executed by a target microprocessor capable of multitasking, records them in a trace memory, and later reads out the trace contents and performs appropriate processing. After summer C
The in-circuit emulator, which is configured to be displayed and analyzed on the RT display screen, compares the instructions executed by the target microprocessor, their addresses, etc. with preset values, and programs a specific address area in memory. A means for generating a signal that becomes active only when the target microprocessor is running, and a means for writing a value in a specific address area of memory by comparing the instructions executed by the target microprocessor and their addresses with preset values. A means for generating a signal that becomes active only when the above two means are active, and a means for sampling and recording in the trace memory the instructions executed by the target microprocessor, their addresses, etc. only when the outputs of the above two means are both active. Equipped with a task trace circuit that can trace only the execution of the function of the task of interest.
JP16226088U 1988-12-14 1988-12-14 Pending JPH0284952U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16226088U JPH0284952U (en) 1988-12-14 1988-12-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16226088U JPH0284952U (en) 1988-12-14 1988-12-14

Publications (1)

Publication Number Publication Date
JPH0284952U true JPH0284952U (en) 1990-07-03

Family

ID=31445926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16226088U Pending JPH0284952U (en) 1988-12-14 1988-12-14

Country Status (1)

Country Link
JP (1) JPH0284952U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5235978A (en) * 1975-09-17 1977-03-18 Hitachi Ltd Manufacturing method of color brow tube fluorecent screen
JPS605355A (en) * 1983-06-23 1985-01-11 Fujitsu Ltd Program route recording device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5235978A (en) * 1975-09-17 1977-03-18 Hitachi Ltd Manufacturing method of color brow tube fluorecent screen
JPS605355A (en) * 1983-06-23 1985-01-11 Fujitsu Ltd Program route recording device

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